Semiconductor Spacer Patterning for High Resolution Lithography
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Solution Overview
Problem
The increasing integration density of semiconductor devices requires higher resolution in lithographic processes, particularly in forming fine photoresist patterns, which is challenging with existing methods that often necessitate precise alignment and multiple exposure processes.
Innovation Solution
A semiconductor structure and method involving the formation of linear core and spacer patterns on a substrate, followed by litho-etch processes to create alternating line patterns in the memory array region and linear features in the peripheral circuit region, allowing for precise pattern formation without the need for multiple exposure alignments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If double patterning technique is used to form fine photoresist patterns, then resolution is improved, but process complexity increases due to requiring two exposure processes with precise alignment
Solution Approach 1:
The patent segments the patterning process into distinct stages: first forming mandrel patterns, then forming spacer patterns around them, and finally removing the mandrels to leave only the spacer patterns. This segmentation allows each stage to be optimized independently, achieving fine resolution through the spacer definition rather than requiring multiple aligned exposures.
Solution Approach 2:
The mandrel patterns are formed in advance as preliminary structures that guide the subsequent spacer formation. These pre-formed mandrels serve as templates that determine the final pattern geometry, allowing the actual functional patterns to be defined by the spacer deposition and etching processes rather than by direct lithographic exposure.
2Productivity
If integration density is increased, then device functionality is improved, but lithographic resolution requirements become more stringent
Solution Approach 1:
The patent transitions from two-dimensional lithographic patterning to three-dimensional spacer formation. By depositing conformal spacer layers around mandrel structures and then anisotropically etching, the final pattern dimensions are determined by vertical film thickness rather than lateral lithographic resolution, effectively moving the critical dimension control to a different dimensional regime.
Solution Approach 2:
The patent changes the controlling parameter for pattern dimension from lithographic wavelength to spacer film thickness. By using atomic layer deposition or chemical vapor deposition to form spacers with controlled thickness, the critical dimensions can be precisely controlled independent of lithographic capabilities, enabling higher integration density.
3Manufacturing precision
If multiple exposure processes are used, then pattern resolution is improved, but manufacturing time increases
Solution Approach 1:
The patent merges multiple patterning operations into a single lithographic exposure step. Instead of performing separate exposures for different pattern layers, the mandrel and spacer patterns are formed in one exposure event, followed by a unified etching process that creates the final integrated pattern structure.
Data Source
AI summary
The present disclosure provide a method for preparing a semiconductor structure. The semiconductor structure includes a substrate having a memory array region and a peripheral circuit region; a plurality of first line patterns positioned in the memory array region and extending along a first direction; a plurality of second line patterns positioned over the first line patterns in the memory array region; and a plurality of linear features positioned in the peripheral circuit region. The plurality of second line patterns extend along a second direction different from the first direction. The plurality of second line patterns and the plurality of linear features are positioned at substantially the same level in the substrate.