High Voltage Semiconductor Device Spacer Masking
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Solution Overview
Problem
High-voltage transistors face challenges in preventing punchthrough phenomena and enhancing breakdown-related characteristics due to the thickness of their gate dielectric layers, which complicates the fabrication process and requires complex mask alignment for impurity region formation.
Innovation Solution
A semiconductor device design featuring a device isolation layer, conductive patterns, spacers, and a gate dielectric layer, where the dummy conductive pattern and spacers serve as a mask for ion implantation and silicidation processes, allowing for the formation of impurity regions without separate mask alignment, thereby simplifying the fabrication process and improving breakdown characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick gate dielectric layer is used in high-voltage transistors, then breakdown characteristics are improved, but punchthrough phenomena occur more easily
Solution Approach 1:
The patent applies different doping concentrations at different locations: heavy doping in LDD regions and lighter doping in DDD regions. This local variation in impurity concentration allows the thick gate dielectric to maintain breakdown voltage while the heavily doped LDD regions prevent punchthrough effects locally where they occur most frequently
Solution Approach 2:
The drain structure combines multiple doped regions (LDD and DDD) with different impurity concentrations and types (n-type and p-type) to create a composite doping profile. This composite structure simultaneously achieves the electrical characteristics needed for both high breakdown voltage and punchthrough prevention
2Reliability
If LDD or DDD structures are implemented to prevent punchthrough and improve breakdown characteristics, then device performance is improved, but fabrication process complexity increases
Solution Approach 1:
The patent forms the LDD and DDD impurity regions in a predetermined sequence before final device completion. By establishing the doping profile early in the fabrication process, subsequent steps can proceed without requiring complex mask alignments, as the doped regions serve as self-aligned references for later processing
Solution Approach 2:
The patent combines the formation of multiple doped regions (LDD and DDD structures) into a unified fabrication approach where impurity implantation steps are integrated with gate and contact formation processes, reducing the total number of separate fabrication steps required
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively mitigates punchthrough phenomena and enhances breakdown-related characteristics by simplifying the fabrication process and reducing the number of required process steps, while maintaining high voltage endurance through the use of a thicker gate dielectric layer.
Implementation Method 1
the dummy conductive pattern and spacers serve as a mask for ion implantation
Implementation Method 2
a gate dielectric layer between the gate conductive pattern and the active region
Data Source
AI summary
The semiconductor device including a device isolation layer disposed in a substrate and defining an active region, a first conductive pattern on the active region, an impurity region in the active region on a side of the first conductive pattern, a second conductive pattern on the active region between the impurity region and the first conductive pattern, a first spacer between the first conductive pattern and the second conductive pattern, and a contact plug disposed on and electrically connected to the first conductive pattern may be provided. The second conductive pattern may have a width less than a width of the contact plug.