Semiconductor Patterning With Spacer Masks for Uniform Fine Circuits
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Solution Overview
Problem
The miniaturization of semiconductor devices increases manufacturing complexity and defect rates due to finer circuit patterns, which existing technologies struggle to address effectively.
Innovation Solution
A method of fabricating semiconductor devices that involves forming specific spacer patterns and mask patterns on a substrate to enhance process margins and integration levels, including the use of slit mask patterns to cover folding regions and eliminate environmental differences between inner and outer patterns, allowing for more uniform and integrated circuit designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If circuit patterns are miniaturized to increase integration, then the number of devices per area increases, but manufacturing complexity and defect rates increase
Solution Approach 1:
The patent divides the pattern formation process into multiple discrete steps using sequential mask patterns (first mask pattern, second mask pattern, third mask pattern) and spacer patterns. Each mask pattern forms a specific portion of the final circuit pattern, allowing complex miniaturized structures to be created through controlled step-by-step patterning rather than attempting to form all patterns in a single step, thereby managing manufacturing complexity while achieving high integration
Solution Approach 2:
The patent introduces vertical dimensionality by forming spacer patterns that extend in the thickness direction from mask patterns. This multi-layered approach allows patterns to be defined in three-dimensional space, enabling higher integration density by utilizing vertical spacing and overlapping structures rather than relying solely on planar miniaturization
2Quantity of substance
If circuit patterns are miniaturized to increase integration, then the number of devices per area increases, but defect rates increase
Solution Approach 1:
The patent applies preliminary protective actions by forming multiple mask patterns and spacer patterns that define precise boundaries and dimensions before final pattern transfer. The first mask pattern and associated spacers prepare the substrate in advance, creating controlled environments for subsequent patterning steps, which reduces the likelihood of defects during miniaturization by pre-establishing accurate pattern geometries
Solution Approach 2:
The patent introduces intermediary spacer patterns between mask patterns and final circuit structures. These spacers act as mediating elements that buffer and control the pattern transfer process, allowing precise dimension control and reducing direct stress on the final miniaturized patterns, thereby lowering defect rates while maintaining high integration
3Manufacturing precision
If multiple mask patterns are formed to increase precision, then manufacturing complexity increases, but manufacturing precision improves
Solution Approach 1:
The patent segments the pattern formation into distinct phases using separate mask patterns for different regions (first mask pattern for first region, second mask pattern for second region, third mask pattern for third region). Each mask pattern is optimized for its specific region, allowing precise control of pattern dimensions and spacing in each area while managing overall process complexity through systematic division of the fabrication sequence
Solution Approach 2:
The patent applies local quality by using different mask patterns and spacer configurations for different regions of the substrate. The first mask pattern and its associated spacers are optimized for the first region, while the second mask pattern and spacers are optimized for the second region, allowing each region to have tailored pattern characteristics that maximize manufacturing precision for that specific area
Data Source
AI summary
A method of fabricating a semiconductor device includes providing a substrate, forming a target film, a first mask film, a second mask film, and an upper mask pattern on the substrate, forming a first spacer pattern that includes a first line portion and a second line portion, and a folding portion that connects the first line portion and the second line portion, forming a slit mask pattern that partially covers the first spacer pattern, forming a first mask pattern by patterning the second mask film using the slit mask pattern and the first spacer pattern as an etching mask, forming a second spacer pattern, forming a second mask pattern by patterning the first mask film using the second spacer pattern as an etching mask, and forming a plurality of target patterns by patterning the target film using the second mask pattern as an etching mask.