Semiconductor Device Fabrication via Spacer Patterning
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Solution Overview
Problem
As semiconductor devices become more highly integrated, it becomes difficult to form fine elements due to increased integration density, which poses challenges in manufacturing and requires efficient methods for pattern formation and etching processes.
Innovation Solution
A method involving the formation of etch target layers, spacer layers, and mask patterns on a substrate with specific etching processes to create fine line-and-space structures, allowing for the formation of reliable and integrated semiconductor devices by controlling the thickness and exposure of layers and patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If integration density of semiconductor devices is increased, then device functionality and capability are improved, but it becomes difficult to form fine elements in the semiconductor devices
Solution Approach 1:
The patent divides the pattern formation process into multiple stages using spacer layers and mask patterns. The spacer layer is formed first, then mask patterns are created on the spacer layer, enabling multi-step patterning that achieves fine element formation while maintaining manufacturing feasibility through systematic process segmentation
Solution Approach 2:
The patent transitions from planar patterning to three-dimensional spacer-based patterning. By forming spacers vertically on mask patterns and using their side surfaces as new patterning references, the method creates fine features in the lateral dimension through vertical structure utilization, enabling higher integration density
2Adaptability or versatility
If integration density is increased, then device capability is improved, but manufacturing complexity increases
Solution Approach 1:
The spacer layer is formed in advance before the actual fine patterning steps. This preliminary structure serves as a foundation for subsequent mask pattern formation and etching processes, simplifying the overall manufacturing sequence by pre-establishing the geometric framework needed for high-density integration
Solution Approach 2:
The spacer layer acts as an intermediary structure between the substrate and the final fine patterns. It mediates the transformation from coarse initial patterns to fine final features through controlled etching and mask formation, reducing the direct complexity of creating fine elements without the spacer intermediary
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the efficient formation of highly integrated semiconductor devices with precise pattern formation, facilitating the creation of fine elements and improving manufacturing processes by ensuring consistent layer thickness and easy polishing, thus overcoming the challenges of increased integration density.
Implementation Method 1
conformally forming a spacer layer on the first patterns and the bulk pattern
Implementation Method 2
etching the spacer layer and the bulk pattern on the peripheral region, using the first mask patterns as an etch mask
Implementation Method 3
polishing the first layer, the spacer layer on the cell region, and the peripheral spacer layer to expose the first patterns and to form cell spacers, peripheral spacers
Implementation Method 4
anisotropically etching the spacers to form openings exposing side surfaces of the first and third patterns
Data Source
AI summary
Methods of fabricating a semiconductor device are provided. The methods may include etching a bulk pattern on a peripheral region to form patterns and then forming a layer on both a cell region and a peripheral region. The methods may include forming line patterns that extend from the cell region onto the peripheral region and then forming a layer on both the cell region and a peripheral region.