Semiconductor Spacer Patterning for CD Uniformity
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Solution Overview
Problem
The spacer patterning technique for semiconductor devices with a 6F2 layout faces challenges in maintaining CD uniformity and process margin due to optical proximity effects and mask CD differences, leading to defects like bridges and degraded CD uniformity in cell block edge regions.
Innovation Solution
A method that involves forming oblique patterns and reverse patterns in the cell and peripheral regions, attaching spacers, and using burying patterns to improve CD uniformity by controlling the deposition, planarization, and etching processes, while reducing pattern density differences and mask CD variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the partition mask is applied to only the cell mat region, then the mask process complexity is reduced, but the CD uniformity in cell block edge regions deteriorates due to optical proximity effects and mask CD differences
Solution Approach 1:
The patent applies different mask patterns to different regions: the cell mat region uses a partition mask with openings, while the peripheral region uses a complementary partition mask with openings. This local differentiation ensures that both regions receive appropriate patterning treatment, preventing CD uniformity degradation in cell block edge regions while maintaining process simplification benefits.
2Productivity
If the spacer patterning technique is used to reduce chip size, then the integration density is improved, but the CD uniformity deteriorates due to optical proximity effects in cell block edge regions
Solution Approach 1:
The patent implements region-specific mask patterns where the cell mat region and peripheral region use complementary partition masks. This local quality approach ensures that cell block edge regions, which are particularly susceptible to optical proximity effects, receive appropriate patterning treatment, thereby maintaining CD uniformity while achieving high integration density through spacer patterning.
3Adaptability or versatility
If the partition mask has different open ratios in different regions, then the patterning flexibility is improved, but the CD uniformity deteriorates due to flare noise during exposure
Solution Approach 1:
The patent changes the mask pattern parameters (opening positions and sizes) differently for the cell mat region and peripheral region. By using complementary partition masks with region-specific opening configurations, the patent achieves the necessary patterning flexibility for different device regions while controlling flare noise effects to maintain CD uniformity across the wafer.
Data Source
AI summary
A method for fabricating a semiconductor device using optical proximity correction to form high integrated cell patterns that are less prone to bridge defects. The method includes: obtaining a target layout of cell patterns, which form rows in a cell region, and peripheral patterns of a peripheral region; forming oblique patterns, which are alternately overlapped in the rows of the cell patterns, and a reverse pattern of the peripheral patterns; attaching spacers to sidewalls of the oblique patterns and the reverse pattern; forming first burying patterns between the oblique patterns and a second burying pattern around the reverse pattern by filling gaps between the spacers; and forming the cell patterns by cutting and dividing the middle portions of the oblique patterns and the first burying patterns, and setting the peripheral pattern with the second burying pattern by removing the reverse pattern.