Fine-Pitch Semiconductor Patterns via Spacer Patterning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor manufacturing techniques face challenges in forming fine patterns with small pitch sizes using copper, as they struggle to create insulating layers with widths corresponding to narrow spaces between wiring lines, limiting the integration density of semiconductor devices.
Innovation Solution
The method involves forming a spacer pattern on a substrate, creating insulating layer patterns adjacent to the spacer, and using a damascene process to form recesses and fill them with conductive material, allowing for precise formation of fine-pitch patterns through chemical mechanical polishing (CMP) to expose the spacer and insulating layers, enabling the formation of conductive lines with uniform width and spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography processes are used to form fine patterns, then the manufacturing process is simple, but the resolution is limited and cannot achieve small pitch sizes
Solution Approach 1:
The patent segments the pattern formation process into multiple steps: first forming a mandrel pattern, then forming spacers around it, and finally creating the final fine pattern. This multi-stage segmentation allows achieving higher resolution than single-step photolithography by breaking down the complex patterning task into manageable stages, each with relaxed resolution requirements.
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional spacer formation. By forming vertical spacers around horizontal mandrels and then using those spacers as new mandrels, the process effectively adds a dimensional aspect that enables achieving smaller pitch sizes than conventional planar photolithography can provide.
2Reliability
If copper is used as wiring material with lower specific resistance, then electrical performance is improved, but forming fine insulating layer patterns with narrow spaces becomes difficult
Solution Approach 1:
The patent performs preliminary actions by first forming the insulating layer pattern with relatively large dimensions using conventional photolithography, then forming spacers that define the final fine-pitch locations. This preliminary patterning with relaxed requirements followed by spacer-based refinement allows the insulating layer to be formed with precision that would be unattainable in a single photolithography step.
Solution Approach 2:
The spacer structure serves as an intermediary element between the initially formed insulating layer pattern and the final fine-pitch copper wiring pattern. This intermediary spacer enables the transition from coarse initial patterning to fine final patterning, resolving the contradiction between using copper for electrical performance and achieving the required pattern precision.
3Productivity
If higher integration density is achieved with fine pitch patterns, then device functionality is improved, but the difficulty of forming narrow insulating layer spaces increases
Solution Approach 1:
The patent segments the challenging single-step fine-pitch insulating layer formation into multiple easier steps: forming a preliminary insulating pattern, forming spacers, and then using those spacers to define the final fine-pitch features. This segmentation transforms a difficult high-integration task into a sequence of manageable steps, each with relaxed manufacturing requirements.
Solution Approach 2:
The spacer structures are self-forming features that automatically define the pitch and spacing of the final patterns through their geometric relationship to the mandrels. This self-service mechanism eliminates the need for additional photolithography steps to define the fine-pitch locations, thereby achieving high integration density without proportionally increasing manufacturing difficulty.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the resolution of photolithography processes, allowing for the creation of finer pitches and improved integration density in semiconductor devices, enabling the production of high-performance, highly integrated semiconductor devices with uniform electric and optical characteristics.
Implementation Method 1
Partially removing a conductive layer may be performed using a chemical mechanical polishing (CMP) process or the like
Data Source
AI summary
Example embodiments may provide fine patterns for semiconductor devices and methods of forming fine patterns for semiconductor devices. Example methods may include forming a spacer pattern on a substrate and/or an insulating layer pattern adjacent to sides of the spacer pattern and/or disposed at the same level as the spacer pattern, forming a pair of recesses exposing sides of the spacer pattern by removing a portion of the insulating layer pattern, and/or filling a conductive material in the recesses.