Semiconductor Spacer Patterning for Finer Lithography Transfer
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Solution Overview
Problem
Existing lithography processes struggle to form fine patterns in semiconductor devices due to issues like bridge formation, breakage, and poor filling quality in corner spaces, making it difficult to meet the requirements of continuously decreasing feature critical dimensions.
Innovation Solution
A preparation method for a semiconductor structure involves providing a structure with a substrate, an etching target layer, a bottom mask layer, and a first mask layer, patterning the first mask layer, forming spacers with vertical sidewall morphology, removing the first mask layer, filling the gap between the spacers with a filling layer having a high etching selectivity ratio, and removing the spacers to form a recess and improve pattern transfer consistency and fineness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing lithography processes are used to form patterns, then the process is simple and direct, but the pattern quality deteriorates with bridge formation, breakage, and poor filling in corner spaces
Solution Approach 1:
The patterning process is divided into multiple stages: first forming a mandrel pattern, then using it as a template to create spacers, removing the mandrel, and repeating the process to form the final pattern. This multi-stage segmentation allows each step to be optimized independently, achieving high pattern quality without excessive overall complexity
Solution Approach 2:
The mandrel structure is formed in advance as a preliminary step before the actual pattern formation. This preliminary action provides a precise template that guides subsequent spacer formation and material deposition, ensuring high pattern quality from the outset rather than attempting correction later
2Quantity of substance
If feature critical dimensions are continuously decreased to increase device density, then device density improves, but pattern formation capability deteriorates due to approaching optical physical limits
Solution Approach 1:
The process transitions from two-dimensional planar patterning to three-dimensional spacer formation with vertical sidewalls. By utilizing the vertical dimension and self-aligned spacer deposition, the method achieves sub-lithographic dimensional control, enabling continued scaling despite optical limits
Solution Approach 2:
The spacer structure forms through self-aligned deposition on the mandrel, automatically defining its position and dimensions without requiring additional alignment steps. This self-service mechanism ensures precise pattern formation at reduced critical dimensions while maintaining manufacturing feasibility
3Manufacturing precision
If spacers with vertical sidewall morphology are formed using the disclosed method, then pattern transfer consistency and fineness improve, but process complexity increases
Solution Approach 1:
The mandrel structure serves as an intermediary template that enables precise spacer formation. This intermediary allows the process to achieve high pattern transfer consistency through self-aligned deposition, while the mandrel can be completely removed afterward, leaving only the desired final pattern without permanent complexity
Data Source
AI summary
A preparation method for a semiconductor structure and a semiconductor structure are provided. Herein, the preparation method comprises: providing a structure to be processed, wherein the structure to be processed comprises a substrate, and an etching target layer, a bottom mask layer and a first mask layer stacked on the substrate; patterning the first mask layer to form a first pattern, the first pattern exposing parts of the bottom mask layer; forming spacers with vertical sidewall morphology on sidewalls of the first mask layer; removing the first mask layer; filling a gap between the spacers with a filling layer, in which a material of the spacers to a material of the filling layer has a high etching selectivity ratio; and removing the spacers.