Semiconductor Fabrication via Spacer Patterning
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Solution Overview
Problem
Current double patterning technologies face challenges in achieving fine patterns without bridge or mask misalignment, particularly as integration density in semiconductor devices increases, requiring more advanced patterning methods.
Innovation Solution
A method involving the formation of multiple mask layers and spacer patterns, with specific etching processes using photoresist patterns and spacers to create interconnections with pad portions and line portions, allowing for precise patterning and overcoming misalignment issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional double patterning technology is used to form fine pitch patterns, then feature size can be reduced beyond photolithography resolution limits, but bridge formation and mask misalignment occur
Solution Approach 1:
The patent segments the patterning process into multiple distinct stages: forming mandrels, depositing first spacers, removing mandrels, depositing second spacers, and selective removal. This multi-stage segmentation allows each step to be optimized independently, preventing bridge formation and misalignment that occur in conventional single-stage processes
Solution Approach 2:
The patent performs preliminary actions by forming mandrels and first spacers before final pattern definition. The mandrels serve as preliminary structures that guide subsequent spacer formation, ensuring precise pattern placement before the actual fine pitch features are created, thereby preventing misalignment
Solution Approach 3:
The patent introduces intermediary structures (mandrels and spacers) that mediate between the photolithography process and final pattern formation. These intermediaries act as temporary guides that enable precise pattern transfer without direct photolithography exposure at the fine pitch level, preventing bridge formation
2Productivity
If integration density of semiconductor device is increased, then device functionality is enhanced, but patterning complexity and misalignment risk increase
Solution Approach 1:
The patent transitions from two-dimensional planar patterning to three-dimensional vertical structure formation using spacers and mandrels. By utilizing the vertical dimension for spacer deposition and selective removal, the process achieves higher integration density while maintaining pattern fidelity, effectively managing patterning complexity
Solution Approach 2:
The patent employs nested structures where spacers are formed around mandrels, and subsequent spacers are formed around previous spacer structures. This nesting approach allows multiple pattern layers to be created systematically, enabling high integration density without proportionally increasing process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the fabrication of highly integrated and reliable semiconductor devices with fine patterns, achieving a pitch smaller than the limitation of conventional photolithography processes while avoiding bridge and misalignment problems.
Implementation Method 1
removing the second line portion and the second connecting portion using the photoresist pattern as an etch mask
Implementation Method 2
forming a first spacer to cover a sidewall of the second mask pattern
Implementation Method 3
the removing of the second line portion and the second connecting portion may be performed using an anisotropic etching process
Implementation Method 4
the partial removing of the first preliminary pad portion may be performed using an isotropic etching process
Data Source
AI summary
Methods of fabricating semiconductor devices are provided including performing two photolithography processes and two spacer processes such that patterns are formed to have a pitch that is smaller than a limitation of photolithography process. Furthermore, line and pad portions are simultaneously defined by performing the photolithography process once and, thus, there is no necessity to perform an additional photolithography process for forming the pad portion. Related devices are also provided.