Semiconductor Patterning via Spacer Technology
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Solution Overview
Problem
The challenge in semiconductor manufacturing is forming fine patterns with varying pitches and densities, particularly in regions with high and low pattern densities, due to limitations in photolithography resolution, which existing patterning methods struggle to address effectively.
Innovation Solution
A method involving the formation of regular and random features using spacer patterning technology (SPT) to create etch masks, allowing for concurrent patterning of regular and random array patterns, and large pitch patterns, improving critical dimension uniformity and process margins by applying SPT to both cell array and core regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography process is used for pattern formation, then manufacturing process is simple, but pattern resolution is limited and cannot form fine patterns with small design rules
Solution Approach 1:
The patterning process is divided into multiple stages: forming mandrels with different pitches in different regions, depositing spacers, selectively removing mandrels, and repeating the process. This segmentation allows each stage to address specific pitch requirements, achieving fine pattern resolution that cannot be obtained through single-step photolithography.
Solution Approach 2:
Mandrels are formed in advance with larger dimensions that can be created using conventional photolithography. These preliminary structures serve as templates for subsequent spacer formation, enabling the creation of finer features through controlled material deposition rather than direct patterning.
2Adaptability or versatility
If conventional patterning method is used, then process is straightforward, but cannot concurrently form patterns with different pitches and densities in different regions
Solution Approach 1:
Different regions of the substrate are assigned different mandrel pitch configurations tailored to their specific requirements. Cell array regions receive mandrels optimized for high-density patterns, while peripheral circuit regions receive mandrels with larger pitches suitable for lower-density structures. This localized optimization enables each region to achieve its optimal pattern density.
Solution Approach 2:
The spacer patterning methodology serves multiple functions: it creates patterns in high-density regions, patterns in low-density regions, and enables pitch multiplication. A single spacer deposition process can simultaneously generate fine features from mandrels of various dimensions, making the process universally applicable across different pattern density requirements.
3Manufacturing precision
If photolithography resolution limit is accepted, then manufacturing is easier, but fine patterns with small design rules cannot be formed
Solution Approach 1:
Spacers act as intermediary structures that translate larger mandrel dimensions into finer final pattern dimensions. The spacer material thickness, controlled by atomic layer deposition with precise thickness control, determines the final critical dimensions. This intermediary approach bypasses photolithography resolution limits by using deposition thickness rather than light exposure to define feature sizes.
Data Source
AI summary
A method for forming patterns of a semiconductor device includes preparing an etch target layer defined with a first region and a second region; forming a regular first feature which is positioned over the etch target layer in the first region and a random feature which is positioned over the etch target layer in the second region; forming a regular second feature over the regular first feature; forming first and second cutting barriers which expose a portion of the random feature, over the random feature; cutting the regular first feature using the regular second feature, to form a regular array feature; cutting the random feature using the first cutting barrier and the second cutting barrier, to form a random array feature; and etching the etch target layer by using the regular array feature and the random array feature, to form a regular array pattern and a random array pattern.