Semiconductor Spacer Layout for Core and Peripheral Region Scaling
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Solution Overview
Problem
As semiconductor devices miniaturize, the spacing between conductive patterns decreases, requiring minimized spacer thickness in core regions, while peripheral regions need optimized spacer thickness to improve performance and mitigate short channel effects.
Innovation Solution
The method involves forming spacers with different total thicknesses on the sidewalls of conductive patterns in core and peripheral regions, using a combination of nitride and oxide spacer layers, with the core spacers being thinner than peripheral spacers to optimize performance and reduce transistor mismatch due to ion implantation variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If spacer thickness is minimized in core regions to accommodate shrinking spacing between conductive patterns, then integration density is improved, but device performance and short channel effect control deteriorate
Solution Approach 1:
The patent applies different spacer thicknesses to different regions of the semiconductor device. Specifically, the first spacers in the core region have a first thickness, while the second spacers in the peripheral region have a second thickness that is greater than the first thickness. This local differentiation allows the core region to achieve high integration density with minimized spacer thickness, while the peripheral region maintains optimized device performance and short channel effect control with increased spacer thickness.
2Ease of manufacture
If uniform spacer thickness is used across all regions, then manufacturing simplicity is maintained, but device performance optimization and short channel effect mitigation worsen
Solution Approach 1:
The patent segments the spacer structure into two distinct parts: first spacers formed in the core region with a first thickness, and second spacers formed in the peripheral region with a second thickness. This segmentation is achieved through a multi-step process involving selective deposition and etching operations that treat different regions differently. The segmentation allows each region to have optimized spacer thickness for its specific functional requirements while maintaining a systematic manufacturing approach.
3Reliability
If spacer thickness is increased in peripheral regions to improve performance gain and short channel effect, then device reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary actions in the form of dummy patterns (first dummy pattern and second dummy pattern) that are formed before the actual spacer deposition. These dummy patterns serve as placeholders that guide the selective formation of spacers with different thicknesses in different regions. The dummy patterns are later removed after serving their purpose, having enabled the complex differential spacer thickness structure to be formed through a systematic process.
Data Source
AI summary
A semiconductor device includes: a substrate including a peripheral region and a core region; a substrate including a peripheral region and a core region; a first conductive pattern disposed over the substrate of the peripheral region; a second conductive pattern disposed over the substrate of the core region; a first spacer structure formed on both sidewalls of the first conductive pattern; and a second spacer structure having a thickness which is smaller than a total thickness of the first spacer structure formed on both sidewalls of the second conductive pattern.