Semiconductor Internal Spacer Segmentation for FinFET Integration
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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices requires finer patterns and reduced sizes, which pose challenges in maintaining operating characteristics and integration reliability, especially with the transition from planar MOSFETs to FinFETs with three-dimensional channels.
Innovation Solution
The semiconductor device incorporates a substrate with active regions and gate structures, featuring channel layers surrounded by gate structures and separated by internal spacers. These spacers include a spacer dielectric layer, a spacer insulating film, and a spacer pile-up film, with optimized thickness and material composition varying based on the source/drain conductivity type.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration of semiconductor devices is increased to meet high performance and high speed demands, then productivity and functionality are improved, but manufacturing precision and reliability deteriorate due to finer patterns and reduced sizes
Solution Approach 1:
The internal spacer is divided into three distinct layers: a first spacer layer in contact with the gate structure, a second spacer layer in contact with the source/drain region, and a third spacer layer between them. This segmentation allows each layer to be optimized for its specific function, with the first and second layers providing electrical isolation and the third layer providing mechanical support and stress management, thereby enabling higher integration while maintaining manufacturing precision
Solution Approach 2:
The internal spacer uses composite material structure with different dielectric materials for each layer. The first and second spacer layers use materials with higher dielectric constants for better electrical isolation, while the third layer uses materials optimized for mechanical properties. This composite approach allows simultaneous optimization of electrical isolation and structural integrity, resolving the contradiction between integration density and manufacturing precision
2Productivity
If the size of planar MOSFET is reduced to increase integration, then productivity is improved, but operating characteristics deteriorate due to size limitations
Solution Approach 1:
The patent transitions from two-dimensional planar MOSFET to three-dimensional FinFET structure with vertical channels. The internal spacer is positioned below the channel layers to provide support and manage stress in the vertical dimension, enabling the channel to maintain appropriate thickness and aspect ratio. This dimensional change allows continued scaling while preserving operating characteristics through improved electrostatic control
Solution Approach 2:
The internal spacer structure is designed beforehand to provide mechanical support and stress management for the thin channel layers. The third spacer layer between the first and second layers acts as a cushioning element that prevents channel layer deformation and manages stress during device operation, thereby maintaining operating characteristics even as device size is reduced for higher integration
3Reliability
If internal spacers are made thinner to improve electrical separation, then reliability is improved, but mechanical stability deteriorates
Solution Approach 1:
The internal spacer is segmented into three layers with distinct functions: the first and second layers provide electrical isolation with adequate thickness for reliability, while the third layer provides mechanical support. This segmentation allows the electrical isolation layers to be optimized for thinness without compromising overall mechanical stability, as the third layer compensates for the reduced thickness
Solution Approach 2:
Different dielectric materials are used for each spacer layer, with the first and second layers using materials optimized for electrical isolation properties and the third layer using materials with superior mechanical properties. This composite material approach allows the internal spacer to achieve both excellent electrical separation and adequate mechanical stability simultaneously
Data Source
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AI summary
A semiconductor device may include a substrate including active regions; gate structures including first and second gate structures intersecting first and second active regions, channel layers on the active regions, surrounded by the gate structures; source/drain regions, connected to channel layers, including a first source/drain region in which the first active region is recessed, having a first conductivity-type, and a second source/drain region in which the second active region is recessed, having a second conductivity-type; internal spacers between the first gate structure and the first source/drain region and between the second gate structure and the second source/drain region, each of the first internal spacers including a spacer insulating film between a spacer dielectric layer and the gate structure, and a thickness of the first internal spacers may be greater than a thickness of the second internal spacers.