Semiconductor Device Leakage Suppression via Spacer Self-Alignment
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Solution Overview
Problem
The challenge in semiconductor device fabrication lies in achieving high integration while minimizing leakage current and addressing mask misalignment issues, which are exacerbated by the need for advanced exposure techniques and increased costs.
Innovation Solution
The semiconductor device design includes word lines and bit lines with strategically placed node contacts and spacers, along with a buried insulation layer and air gaps, to align sidewalls and maintain uniform distances, reducing leakage current and improving integration by using double patterning technology for separation patterns, thereby reducing fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If new and expensive exposure techniques are used for fine patterns, then manufacturing precision is improved, but device complexity and fabrication cost increase
Solution Approach 1:
The fabrication process is divided into two distinct stages: first forming word lines and bit line node contacts using conventional exposure techniques, then forming bit lines and storage node contacts using spacer-based self-alignment. This segmentation allows each stage to use appropriate fabrication methods, avoiding the need for expensive EUV exposure for all patterns.
Solution Approach 2:
Word lines and bit line node contacts are formed in advance before the bit lines and storage node contacts. The pre-formed structures serve as alignment references for subsequent spacer deposition, enabling precise positioning of remaining components without requiring high-precision exposure for all elements.
2Productivity
If pattern widths and spaces are reduced for higher integration, then productivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The spacer structures automatically self-align to the pre-formed word lines and bit line node contacts, and the bit lines self-align to the storage node contacts through the spacer positioning. This self-alignment mechanism eliminates the need for complex mask alignment procedures, enabling high integration density while maintaining manufacturing feasibility with conventional exposure techniques.
3Manufacturing precision
If mask misalignment is addressed through conventional methods, then manufacturing precision is improved, but device complexity and fabrication cost increase
Solution Approach 1:
Spacer structures serve as intermediary elements between the pre-formed components (word lines, bit line node contacts) and the components to be formed (bit lines, storage node contacts). These spacers act as physical templates that automatically define the positions and dimensions of subsequent patterns, eliminating mask misalignment issues without requiring complex alignment procedures.
Data Source
AI summary
A semiconductor device includes a plurality of word lines; a plurality of bit lines; and a plurality of bit line node contacts. The plurality of word lines extend in a first direction in or on a substrate. The plurality of bit lines crosses over the plurality of word lines. Each of the plurality of bit line node contacts connects a corresponding bit line to the substrate, and each of the plurality of bit line node contacts has a width substantially equal to a width of the corresponding bit line.