Semiconductor Spacer Fabrication with Silicon Ion Implantation
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high reliability, performance, and integration density while maintaining low power consumption and multifunctionality, particularly in field effect transistors, due to limitations in spacer materials and etch selectivity.
Innovation Solution
The fabrication method involves forming spacers with a nitride-based low-k insulating layer and injecting silicon ions to create regions with varying silicon concentrations, enhancing etch selectivity and reducing parasitic capacitance, allowing for improved electric characteristics and process margins in semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional spacer materials are used, then manufacturing is simple, but etch selectivity is insufficient
Solution Approach 1:
The spacer is divided into multiple portions (first portion adjacent to gate pattern, second portion spaced apart) with different silicon concentrations. This segmentation allows each portion to have optimized properties: the first portion provides etch resistance near the gate, while the second portion enables selective exposure for contact hole formation, thereby improving etch selectivity without requiring entirely new materials.
Solution Approach 2:
Different regions of the spacer are given different silicon concentrations to achieve local optimization. The first portion has a silicon concentration of 30-40 at% for high etch resistance, while the second portion has higher silicon concentration for selective etching. This local quality differentiation resolves the contradiction by providing tailored properties in different locations rather than uniform properties throughout.
2Manufacturing precision
If uniform spacer structure is used, then manufacturing is easy, but contact hole formation selectivity is poor
Solution Approach 1:
The spacer structure is prepared in advance with distinct first and second portions having different silicon concentrations before contact hole formation. The second portion is specifically designed to be exposed and have higher etch selectivity, so that when contact holes are formed, the etching process can selectively remove the interlayer insulating layer exposed at the second portion while the first portion remains protected. This preliminary structuring enables precise contact hole formation without adding complex subsequent steps.
3Reliability
If high-k insulating material is used for spacers, then dielectric strength is high, but parasitic capacitance increases
Solution Approach 1:
The spacer is constructed as a composite structure with different silicon concentrations in different portions. The nitride-based low-k insulating layer with silicon ion injection creates a composite material that maintains dielectric strength while reducing parasitic capacitance. The specific silicon concentration range (30-40 at%) optimizes the balance between dielectric properties and capacitance, resolving the contradiction by using composite rather than uniform material composition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in semiconductor devices with enhanced electric characteristics, improved etch resistance, and increased process margins, enabling faster operation and higher performance while maintaining low power consumption.
Implementation Method 1
injecting silicon ions into the spacer layer
Data Source
AI summary
Methods of fabricating a semiconductor device include forming a gate pattern on a substrate, forming spacers to cover both sidewalls of the gate pattern, forming an interlayer insulating layer to cover the gate pattern and the spacers, and forming contact holes to penetrate the interlayer insulating layer and expose sidewalls of the spacers. The forming of the spacers includes forming a spacer layer to cover the gate pattern and injecting silicon ions into the spacer layer. The spacer layer is a nitride-based low-k insulating layer, whose dielectric constant is lower than that of silicon oxide.