Semiconductor Spacer Patterning for Sub-60 nm Patterns
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Solution Overview
Problem
Conventional Spacer Patterning Technology (SPT) is limited in forming fine patterns with varying critical dimensions due to uniform spacer thickness, making it difficult to achieve patterns smaller than 60 nm in semiconductor devices.
Innovation Solution
The method involves forming spacers at different levels with varying thicknesses using Multi Exposure Technology (MET), where sacrificial patterns and spacers with different etching selectivities are used to create spacers on sidewalls, allowing for the formation of patterns with multiple widths and pitches by adjusting the spacer thicknesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional SPT with uniform spacer thickness is used, then the manufacturing process is simple, but the pattern size is limited to at least 60 nm and cannot form patterns smaller than this
Solution Approach 1:
The patent divides the spacer formation process into multiple segments by performing photo lithography multiple times (multi-exposure) to create sacrificial patterns at different levels. Each exposure creates a specific spacer thickness, allowing the final structure to have spacers with different thicknesses corresponding to different pattern sizes. This segmentation enables precise control of pattern dimensions while maintaining the simplicity of the basic spacer patterning approach.
Solution Approach 2:
The patent introduces a vertical dimension (z-axis) to the traditional two-dimensional spacer patterning by forming sacrificial patterns at different heights through multi-exposure. This creates a three-dimensional structure where spacers at different levels have different thicknesses, enabling the formation of patterns with varying critical dimensions in a single etching process.
2Manufacturing precision
If photo lithography is used to form finer patterns, then the wavelength of light must be reduced or lens size enlarged, but currently available light sources (KrF, ArF) cannot form patterns smaller than 60 nm
Solution Approach 1:
The patent introduces spacers as intermediary structures that mediate between the photo lithography process and the final pattern formation. By using spacers formed on sacrificial patterns as etching masks, the process bypasses the resolution limits of conventional photo lithography. The spacer thickness, controlled by deposition processes rather than light wavelength, determines the final pattern size, enabling sub-60 nm feature fabrication with existing light sources.
Solution Approach 2:
The patent changes the controlling parameter for pattern size from optical parameters (wavelength, numerical aperture) to deposition parameters (spacer thickness). By controlling the thickness of spacers through deposition processes and using multi-exposure to create different spacer thicknesses, the method achieves fine pattern formation without being constrained by the resolution limits of available photolithography light sources.
3Manufacturing precision
If Double Patterning is used to form patterns, then photo resist patterns are used as etching masks twice, but this cannot achieve the same level of fineness as Spacer Patterning Technology
Solution Approach 1:
The patent uses spacers as copies of the sacrificial pattern sidewalls, creating precise replicas that define the final pattern dimensions. The spacer thickness directly copies the desired pattern width, providing a more accurate and controllable method than using photo resist patterns as masks. This copying mechanism through spacer formation enables superior pattern fidelity and fineness compared to conventional double patterning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of semiconductor devices with fine patterns having various critical dimensions and sizes, overcoming the limitations of conventional SPT by allowing for the creation of patterns smaller than 60 nm and improving integration density.
Implementation Method 1
after a spacer 6 is form on sidewalls of the photoresist pattern 4
Implementation Method 2
the photoresist exposed by a photomask becomes soluble and can be easily removed by the developer chemical used in a developing process
Implementation Method 3
the etching target layer 2 is etched by using the spacer 6 as an etching mask
Data Source
AI summary
A method for manufacturing a semiconductor device which includes fine patterns having various critical dimensions (CDs) by adjusting a thickness of spacer used as an etching mask in Spacer Patterning Technology (SPT). The method for manufacturing a semiconductor device includes forming spacers at a different level over an etching target layer and etching the etching target layer exposed among the spacers.