Semiconductor Device Spacer Thickness Control
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Solution Overview
Problem
In semiconductor manufacturing, the Short Channel Effect (SCE) affects device performance, particularly in System-On-a-Chip (SOC) designs where a smaller thermal budget is required to control SCE, leading to reduced reliability of I/O devices due to a smaller overlapping area of the Lightly Doped Drain (LDD) and channel regions.
Innovation Solution
A method for manufacturing semiconductor devices involves providing a substrate structure with dummy gate structures and spacer layers, where the first dummy gate is removed, and the spacer layer is etched back to reduce its thickness, allowing for the formation of trenches and subsequent deposition of gate dielectric and gate materials, thereby increasing the overlapping area of the LDD and channel regions without adding to the thermal budget.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a smaller thermal budget is used to control short channel effect, then gate control ability is improved, but the overlapping area of LDD region and channel region becomes smaller, reducing device reliability
Solution Approach 1:
The substrate is divided into first device region (I/O device) and second device region (core device), allowing different thermal budgets to be applied to different regions. The first dummy gate structure and second dummy gate structure are formed separately, enabling independent processing and thermal management for each device type.
Solution Approach 2:
Different thermal budgets are applied locally to different device regions. The I/O device region receives a larger thermal budget to ensure adequate LDD-channel overlapping area and reliability, while the core device region receives a smaller thermal budget to control short channel effect, allowing each region to have optimized properties for its specific function.
2Reliability
If different thermal budgets are applied to different device regions, then device-specific performance is optimized, but manufacturing process complexity increases
Solution Approach 1:
Dummy gate structures are formed preliminarily before actual gate formation. These dummy gates serve as placeholders that enable subsequent selective removal and independent thermal processing of different device regions. The dummy gate structures include dummy gate dielectric layers and spacer layers that facilitate the differential thermal budget application.
Solution Approach 2:
The dummy gate structures act as intermediary elements that enable the transition from uniform processing to differential processing. By forming dummy gates first, the patent creates a structure that can be selectively modified in different regions, serving as a mediator between the requirement for uniform manufacturing and the need for region-specific optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of semiconductor devices by increasing the overlapping area of the LDD and channel regions, improving device performance without increasing the thermal budget, thus addressing the reliability issues associated with smaller thermal budgets.
Implementation Method 1
etching back the spacer layer, so as to reduce thickness of the spacer layer
Implementation Method 2
removing exposed dummy gate dielectric layer, so as to from a trench
Implementation Method 3
depositing a gate dielectric layer to cover a bottom portion and a side wall of the first trench and a bottom portion and a side wall of the second trench
Data Source
AI summary
The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The method includes: providing a substrate structure, where the substrate structure includes: a substrate having a first device region and a second device region, a first dummy gate structure at the first device region, a second dummy gate structure at the second device region, and an LDD region below the first dummy gate structure. The first dummy gate structure includes a first dummy gate dielectric layer at the first device region, a first dummy gate on the first dummy gate dielectric layer, and a first spacer layer at a side wall of the first dummy gate. The second dummy gate structure includes a second dummy gate dielectric layer at the second device region, a second dummy gate on the second dummy gate dielectric layer, and a second spacer layer at a side wall of the second dummy gate. The method further includes removing the first dummy gate; etching back the first spacer layer to reduce a thickness of the first spacer layer; removing an exposed portion of the first dummy gate dielectric layer to form a first trench; and removing the second dummy gate and exposed second dummy gate dielectric layer to form a second trench.