Semiconductor Chip Spacer Design for Through Hole Positional Accuracy
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Solution Overview
Problem
The existing semiconductor devices used for deflecting charged particle beams face challenges in arranging through holes with high positional accuracy, particularly when the number of holes increases or the deflector size decreases, leading to potential warping of the semiconductor chip due to thermal stress, which affects the precision of electron beam deflection.
Innovation Solution
A semiconductor device design that includes a semiconductor chip with through holes, a substrate with a resin or ceramic, a spacer with a second opening larger than the chip region, and bonding materials with specific thermal expansion coefficients and thicknesses to alleviate stress and maintain positional accuracy of the through holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of through holes increases or the deflector size decreases, then the deflection capability improves, but the positional accuracy of through holes deteriorates due to chip warping
Solution Approach 1:
The patent divides the bonding structure into multiple segments: a first bonding region with first bonding material and a second bonding region with second bonding material. This segmentation allows different regions to have different thermal expansion characteristics, compensating for warping stresses and maintaining through-hole positional accuracy while supporting higher density configurations
Solution Approach 2:
The patent changes the thermal expansion parameter by using bonding materials with different thermal expansion coefficients in different regions. The first bonding material has a thermal expansion coefficient matched to the semiconductor chip, while the second bonding material has a thermal expansion coefficient matched to the substrate, creating a gradient that accommodates thermal stresses during heating processes
2Strength
If thermal stress is applied during heating, then the bonding strength improves, but the warp amount of semiconductor chip increases
Solution Approach 1:
The patent applies local quality by providing different bonding materials with different thermal expansion coefficients in different local regions. The first bonding material in the first bonding region has thermal expansion characteristics matched to the semiconductor chip, while the second bonding material in the second bonding region has characteristics matched to the substrate, allowing each region to handle thermal stress appropriately
Solution Approach 2:
The patent introduces an intermediary approach by using two different bonding materials as mediators between the semiconductor chip and substrate. These bonding materials act as transition layers that gradually transfer thermal expansion stresses, preventing sudden stress concentration that would cause warping while still achieving strong bonding
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces the warp amount of the semiconductor chip during thermal processes, ensuring high positional accuracy of through holes and improving the deflection precision of electron beams by using a spacer with a lower thermal expansion coefficient and sufficient thickness to cushion thermal contraction stress.
Implementation Method 1
a spacer (30) provided between the semiconductor chip (10) and the substrate (20}, the spacer (30) having a second opening (31) larger than the region (14); a first bond (40) provided between the semiconductor chip (10) and the spacer (30); and a second bond (42) provided between the spacer (30) and the substrate (20)
Data Source
AI summary
A semiconductor device according to an embodiment includes a semiconductor chip including a region having through holes; a substrate having a first opening larger than the region, the substrate containing a resin or a ceramic; a spacer provided between the semiconductor chip and the substrate, the spacer having a second opening larger than the region; a first bond provided between the semiconductor chip and the spacer; and a second bond provided between the spacer and the substrate.