Semiconductor Spacer for Transistor Isolation
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Solution Overview
Problem
The development of three-dimensional transistor structures faces challenges due to the limitations of middle dielectric isolation (MDI) thickness, which is often compromised by voids and residues generated during the replacement-metal-gate (RMG) process, and the difficulty in forming a bottom dielectric isolation (BDI) due to the critical thickness of sacrificial layers with high germanium concentration.
Innovation Solution
The use of a semiconductor spacer, composed of silicon free of nitrogen, carbon, oxygen, and germanium, is introduced between the upper and lower transistors, allowing for a thicker separation than conventional MDI and facilitating the formation of a bottom isolation region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If middle dielectric isolation (MDI) is used to separate upper and lower transistors, then transistor separation is achieved, but the MDI thickness is compromised by voids and residues generated during the replacement-metal-gate (RMG) process
Solution Approach 1:
The patent changes the material parameter from silicon-nitride MDI to semiconductor spacer material, and changes the thickness parameter from thin (compromised by RMG process) to thick (exceeding individual channel layer thicknesses). This parameter change eliminates the voids and residues problem while maintaining separation functionality.
Solution Approach 2:
The patent extracts the problematic RMG process from the MDI formation sequence by using a semiconductor spacer that is formed independently of the sacrificial gate replacement process. This eliminates the source of voids and residues that plague conventional MDI formation.
2Ease of manufacture
If sacrificial layers with high germanium concentration are used in the RMG process, then gate replacement is enabled, but the critical thickness makes it difficult to form bottom dielectric isolation (BDI)
Solution Approach 1:
The patent segments the isolation structure into two distinct parts: a semiconductor spacer between transistors and a separate BDI region at the bottom. This segmentation allows the BDI to be formed independently with appropriate thickness, uncoupled from the critical thickness constraints of the sacrificial layers needed for RMG.
Solution Approach 2:
The semiconductor spacer acts as an intermediary structure that fulfills the separation function without interfering with BDI formation. Its presence allows the BDI to be formed with sufficient thickness despite the presence of high-germanium sacrificial layers, as the spacer provides the necessary electrical isolation without compromising BDI integrity.
3Reliability
If conventional MDI thickness is used, then transistor isolation is provided, but the thickness is insufficient compared to the semiconductor spacer thickness that exceeds individual channel layer thicknesses
Solution Approach 1:
The patent changes the thickness parameter from conventional MDI (thin, comparable to or thinner than channel layers) to semiconductor spacer thickness (thicker than individual channel layers). This parameter change simultaneously improves isolation reliability and provides sufficient physical separation for device performance.
Data Source
Figure 1A
Figure 1B
Figure 2A~2B
AI summary
Transistor devices are provided. A transistor device includes a substrate and a transistor stack on the substrate. The transistor stack includes a lower transistor and an upper transistor that is on top of the lower transistor. Moreover, the transistor device includes a semiconductor spacer between the upper transistor and the lower transistor. Related methods of forming transistor devices are also provided.