Semiconductor Spacer Via Structure for BEOL Short-Circuit Prevention
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Solution Overview
Problem
The increasing device density in integrated circuits leads to a short-circuit risk between metal lines and under-layer vias due to the small horizontal space margin, which existing technologies struggle to address effectively, particularly in the back-end-of-line (BEOL) structure of semiconductor devices.
Innovation Solution
A connection structure for integrated circuits is introduced, featuring a spacer via structure where an insulation material forms a spacer on the side surface of the via hole, increasing the horizontal space margin between the via and the metal line, thereby reducing the risk of short circuits. This structure includes a 1st metal line, a 2nd layer with a via, and a 3rd layer with a metal line connected through the spacer via, where the spacer is formed on the upper side surface of the via hole, and the via has a unique geometry with a smaller bottom surface width compared to the top surface width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device density is increased to improve integration, then productivity and circuit functionality are improved, but the horizontal space margin between metal lines and under-layer vias decreases, increasing short-circuit risk
Solution Approach 1:
The patent introduces a spacer structure that adds a lateral dimension to the via configuration. By forming insulating spacers on the sidewalls of the via hole, the effective horizontal clearance between the via and adjacent metal lines is increased without reducing the via's vertical connection function. This dimensional addition resolves the contradiction by maintaining reliability while preserving high device density.
Solution Approach 2:
The spacer structure acts as an intermediary insulating element positioned between the conductive via and the adjacent metal line. This intermediate structure provides electrical isolation and prevents short circuits, thereby maintaining reliability without compromising the high device density achieved through increased integration.
2Productivity
If via hole size is reduced to increase device density, then productivity is improved, but manufacturing precision and alignment accuracy deteriorate
Solution Approach 1:
The spacer structure compensates for the reduced via dimensions by adding lateral insulation thickness. This allows the via hole to maintain a smaller footprint for higher density while the spacer provides the necessary manufacturing tolerance buffer, thereby preserving alignment accuracy despite the reduced via size.
Solution Approach 2:
The spacer structure serves as a pre-formed protective cushion around the via hole. This cushioning structure anticipates and compensates for potential alignment variations during manufacturing, ensuring that even with reduced via dimensions, the alignment accuracy and manufacturing precision are maintained.
3Productivity
If via aspect ratio is increased to reduce via hole size, then device density is improved, but void formation and misconnection risks increase
Solution Approach 1:
The spacer structure adds lateral dimension to the via configuration, which helps distribute stress and prevents void formation in high aspect ratio vias. By providing lateral support and insulation, the spacer enables the via to maintain a higher aspect ratio for increased device density without compromising reliability through void formation or misconnection.
Data Source
AI summary
A connection structure for an integrated circuit includes: a 1st layer including a 1st metal line; a 2nd layer, above the 1st layer, including a 1st via; and a 3rd layer, above the 2nd layer, including a 2nd metal line connected to the 1st metal line through the 1st via, wherein the 1st via comprises a spacer structure at a side of an upper portion of the 1st via, the spacer structure comprising an insulation material.