Gate-All-Around Semiconductor Structure for Speed and Stress Resistance
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Solution Overview
Problem
Semiconductor display devices face challenges in achieving high-speed operation and high stress resistance, particularly in reducing bezel width and enhancing pixel density while maintaining high definition and resolution, especially with the use of flexible substrates.
Innovation Solution
The semiconductor device design includes a semiconductor film with a channel formation region and impurity regions, covered by insulating films and gate electrodes, allowing for increased carrier flow and reduced contact resistance, and is fabricated using a method that ensures high crystallinity and flexibility, enabling high-speed operation and stress resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a flexible substrate is used to widen application range, then adaptability is improved, but stress resistance deteriorates
Solution Approach 1:
The patent employs a composite structure combining a flexible substrate with a carefully engineered semiconductor device stack including buffer layers, semiconductor layers, insulating films, and electrode structures. This composite construction allows the device to maintain structural integrity and electrical performance while adapting to the mechanical flexibility of the substrate, thereby resolving the contradiction between adaptability and stress resistance.
2Measurement precision
If pixel density is increased to achieve higher definition, then display quality is improved, but operating speed deteriorates due to higher frequency requirements
Solution Approach 1:
The patent optimizes multiple parameters including the thickness and composition of semiconductor layers, doping concentrations, and electrode configurations to reduce resistance and improve carrier mobility. These parameter changes enable the device to operate at higher frequencies required for high pixel density displays while maintaining adequate operating speed through improved electrical characteristics.
3Area of stationary object
If driver circuits are integrated on the same substrate to narrow bezel width, then device area is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent integrates driver circuits, pixel portions, and signal line driver circuits onto a single substrate, merging multiple functional components into one unified structure. This integration reduces the overall device area and bezel width while the standardized manufacturing process and material selection help manage the increased manufacturing complexity through process consolidation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables semiconductor devices to operate at high speeds with increased field-effect mobility and stress resistance, supporting high-resolution displays and flexible substrate applications.
Implementation Method 1
a gate electrode overlapping the side and top portions of the semiconductor film in the channel formation region with the insulating film positioned between the gate electrode and the side and top portions
Implementation Method 2
a source electrode and a drain electrode in contact with side and top portions of the semiconductor film in the pair of impurity regions
Data Source
AI summary
A semiconductor device that can operate at high speed or having high strength against stress is provided. One embodiment of the present invention is a semiconductor device including a semiconductor film including a channel formation region and a pair of impurity regions between which the channel formation region is positioned; a gate electrode overlapping side and top portions of the channel formation region with an insulating film positioned between the gate electrode and the side and top portions; and a source electrode and a drain electrode in contact with side and top portions of the pair of impurity regions.