Semiconductor Memory Stabilizing Voltage via Shared Circuit

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Solution Overview

Problem

Semiconductor memory devices face challenges in reducing power consumption and improving area efficiency while generating internal stabilizing voltages for data storage regions.

Innovation Solution

The semiconductor memory device incorporates multiple capacitor groups arranged adjacent to data storage regions, each receiving an internal voltage from a voltage-generating circuit to provide stabilizing voltages, thereby reducing power consumption and enhancing area efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple separate voltage-generating circuits are used for each data storage region, then each region receives adequate stabilizing voltage, but device complexity and area increase

Engineering Contradiction:
Improvestabilizing voltage provisionVSAvoidcircuit configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges multiple voltage-generating circuits into a single shared voltage-generating circuit that serves all data storage regions (first through fourth data storage regions). This single circuit generates internal voltage that is distributed to multiple capacitor groups, each located adjacent to different data storage regions. The merging approach maintains reliable stabilizing voltage provision to all regions while reducing overall device complexity and area compared to having separate circuits for each region.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent segments the voltage distribution function by placing multiple capacitor groups at different locations adjacent to different data storage regions. Each capacitor group receives voltage from the shared voltage-generating circuit and locally provides stabilizing voltage to its adjacent data storage region. This segmentation enables efficient local voltage distribution while using a centralized voltage generation approach.

Inventive Principle:
Principle #1Segmentation

2Area of stationary object

If internal circuits area is reduced to improve area efficiency, then area efficiency improves, but power consumption management becomes more challenging

Engineering Contradiction:
Improveinternal circuits areaVSAvoidpower consumption
Core Design Contradiction:
Area of stationary objectVSUse of energy by moving object

Solution Approach 1:

The patent uses capacitor groups that are pre-charged with stabilizing voltage from the voltage-generating circuit. These capacitors store energy in advance and provide stabilizing voltage to data storage regions during operation, reducing the need for continuous power supply and enabling more efficient power management in compact internal circuits with reduced area.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration allows for efficient transmission of stabilizing voltages to data storage regions using capacitors, reducing power consumption and improving area efficiency in semiconductor memory devices.

Implementation Method 1

Each of the capacitor groups may include a plurality of capacitors

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS10332578B2Semiconductor device
Publication Date: 2019.06.25 SK HYNIX INC
  • US10332578B2 patent drawing
  • US10332578B2 patent drawing
  • US10332578B2 patent drawing

AI summary

A semiconductor memory device may include first to fourth data storage regions. The semiconductor memory device may include a first to fourth capacitor groups and a voltage-generating circuit. The first capacitor group may be arranged adjacent to the first data storage region to provide the first data storage region with a first stabilizing voltage. The second capacitor group may be arranged adjacent to the second data storage region to provide the second data storage region with a second stabilizing voltage. The third capacitor group may be arranged adjacent to the third data storage region to provide the third data storage region with a third stabilizing voltage. The fourth capacitor group may be arranged adjacent to the fourth data storage region to provide the fourth data storage region with a fourth stabilizing voltage. The voltage-generating circuit may be configured to provide the first to fourth capacitor groups with an internal voltage.