Semiconductor Stack Layout for Balanced Gold Wire Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor stack structures, significant length differences between gold wires connected to different ranks can cause signal reflection, leading to poor performance due to unbalanced on-die termination (ODT) activation, affecting adjacent ranks and degrading the packaging substrate's electrical performance.
Innovation Solution
The semiconductor stack structure arranges semiconductor dies such that each pair of adjacent dies in the same signal channel are connected to the same connection pad, reducing the length difference between gold wires and minimizing signal reflection by staggered stacking and the use of isolation attach films with varying elastic moduli to manage heat and warping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor dies are stacked and connected to the same connection pad, then the integration density is improved, but the length difference between gold wires causes signal reflection and degrades electrical performance
Solution Approach 1:
The patent divides the connection structure into segmented regions by positioning different semiconductor dies in distinct channel regions (first channel region and second channel region) around the connection pad. This segmentation allows for controlled gold wire routing that minimizes length differences between parallel circuits, thereby reducing signal reflection while maintaining high integration density through multi-die stacking.
2Area of stationary object
If semiconductor dies are arranged in a stack structure, then the packaging substrate's space utilization is improved, but signal reflection from unbalanced ODT activation affects adjacent ranks and degrades performance
Solution Approach 1:
The patent applies local quality by assigning specific semiconductor dies to specific channel regions based on their signal characteristics. Dies in the first channel region and second channel region are positioned to create balanced gold wire lengths to the connection pad, locally optimizing the electrical path for each rank while maintaining the overall stacked architecture for high space utilization.
3Adaptability or versatility
If gold wires of different lengths are used to connect dies to the same connection pad, then the flexibility in die arrangement is improved, but signal reflection increases and electrical performance deteriorates
Solution Approach 1:
The patent employs asymmetric positioning of semiconductor dies relative to the connection pad, placing dies in different channel regions (first and second channel regions) at strategically different locations. This asymmetric arrangement creates balanced gold wire lengths despite the asymmetric physical positions, allowing flexible die arrangement while minimizing signal reflection through careful geometric optimization.
Data Source
AI summary
A semiconductor stack structure at least includes: a substrate; connection pads located on a surface of the substrate; and a plurality of semiconductor dies located on the surface of the substrate and stacked in sequence in a first direction, the first direction being a thickness direction of the substrate. Each two adjacent semiconductor dies located in a same signal channel are connected to a same connection pad, and two semiconductor dies connected to a same connection pad are respectively located in a first channel region and a second channel region of a signal channel.