Semiconductor Stack Packages Using Interposer and Protection Layers

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Solution Overview

Problem

Existing semiconductor stack package fabrication methods face challenges in efficiently stacking additional semiconductor chips between a chip stack and a package substrate, requiring complex processes and precise control, which can lead to mechanical stress and reliability issues.

Innovation Solution

The method involves using an interposer with through electrodes to vertically stack semiconductor chips, allowing for the insertion of additional chips on both surfaces, with protection layers to alleviate stress and improve handling, enabling reliable electrical connections and simplified fabrication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If additional semiconductor chips are stacked between the chip stack and package substrate using existing methods, then the functionality and capacity of the package is improved, but the process complexity and mechanical stress increase significantly

Engineering Contradiction:

Improvechip stacking capabilityVSAvoidfabrication process complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces an interposer as an intermediary substrate between the semiconductor chip stack and the package substrate. This interposer simplifies the fabrication process by providing a standardized platform for stacking additional chips, reducing the complexity of direct integration while enabling enhanced functionality and adaptability.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

Engineering Contradiction:

Improvechip stacking capabilityVSAvoidpackage reliability

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent employs protection layers as cushioning structures that are formed beforehand to cover and protect the semiconductor chip stacks. These protection layers alleviate mechanical stress during the stacking process and improve the overall reliability of the package by preventing stress concentration and potential failure points.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

3Adaptability or versatility

If existing fabrication methods are used to stack additional chips, then chip stacking is achieved, but excessive heat and pressure are required increasing fabrication costs

Engineering Contradiction:

Improvechip stacking capabilityVSAvoidfabrication ease

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent divides the stacking process into separate, manageable stages using the interposer as a modular platform. This segmentation allows additional chips to be stacked without requiring excessive heat and pressure in a single complex operation, thereby reducing fabrication costs and improving ease of manufacture while maintaining adaptability.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS9299689B2Methods of fabricating semiconductor stack packages

Publication Date: 2016.03.29 SK HYNIX INC

AI summary

Semiconductor chip stacks are provided. The semiconductor chip stack includes a semiconductor chip stack including a plurality of first semiconductor chips vertically stacked on a top surface of the interposer, a second semiconductor chip stacked on a bottom surface of the interposer opposite to the semiconductor chip stack, and an external electrode attached to a top surface of the second semiconductor chip opposite to the interposer. Electronic systems including the semiconductor chip stack and related methods are also provided.