Semiconductor Stack with Lateral Passivation for Wafer Bonding
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Solution Overview
Problem
Conventional wafer-to-wafer bonding techniques face issues with yield degradation due to differences in upper and lower wafers, position discrepancies of known good dies, and instability in fine pitch processes, leading to defective semiconductor stacks and suboptimal bonding interfaces.
Innovation Solution
A semiconductor stack design where only defect-free upper chips are sorted and attached to a carrier wafer with an upper lateral-side passivation layer, enabling a flat bonding interface and enhanced rolled throughput yield, and allowing for hetero bonding between different chip types through redistribution layers and smart cutting or stealth cutting of the carrier wafer without adhesives.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional wafer-to-wafer bonding is used with upper and lower wafers having the same chip size and arrangement, then the bonding process is simple, but yield degradation occurs due to yield differences and position differences of known good dies
Solution Approach 1:
The invention segments the bonding process into two distinct stages: first bonding the lower wafer to the carrier, then bonding the upper wafer to the lower wafer. This segmentation allows independent optimization of each bonding interface, enabling the lower wafer to be bonded with proper alignment while the upper wafer can be bonded without strict position matching requirements, thus maintaining simplicity while improving yield
Solution Approach 2:
The invention introduces a carrier wafer as an intermediary component between the lower and upper wafers. The carrier serves as a stable base for bonding the lower wafer, and provides a flat bonding interface for the upper wafer. This intermediary structure decouples the position requirements of the two wafers, allowing independent optimization and eliminating yield degradation from position mismatches
2Reliability
If die-to-wafer technology is applied to avoid accumulated failure, then only known good dies can be sorted and attached, but process stability for fine pitch is degraded
Solution Approach 1:
The invention applies partial sorting - only the lower wafer undergoes strict known good die sorting and alignment, while the upper wafer can be bonded with more relaxed requirements. This partial application of sorting criteria maintains process stability for fine pitch while still eliminating accumulated failures from the critical lower interface
3Ease of manufacture
If D2W collective bonding is carried out with adhesive, then chips can be attached, but a flat bonding interface cannot be formed due to adhesive height difference
Solution Approach 1:
The invention extracts and removes the adhesive layer from the bonding process. By bonding the upper wafer directly to the lower wafer without adhesive, the height difference problem is eliminated, achieving a flat bonding interface while maintaining chip attachment capability through direct wafer bonding
Data Source
AI summary
A semiconductor stack and a method for manufacturing the same are disclosed. The semiconductor stack includes a lower chip, an upper chip disposed over the lower chip, an upper lateral-side passivation layer surrounding side surfaces of the upper chip, and a plurality of bonding pads and a bonding passivation layer disposed between the upper chip and the lower chip.