3D Semiconductor Stack Structure for Reliable Memory Cell Integration
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Solution Overview
Problem
The integration of semiconductor devices is limited by the area occupied by unit memory cells, and existing three-dimensional semiconductor devices face challenges in improving operational reliability.
Innovation Solution
A semiconductor device with a stack structure comprising alternately stacked insulating and sacrificial layers, a channel pattern, a transistor, and a contact structure that electrically connects the peripheral circuit to the channel pattern, along with a gate structure and source patterns, is proposed. This structure enhances the device's stability and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If three-dimensional semiconductor devices are used to improve integration, then the area occupied by unit memory cells is reduced, but operational reliability deteriorates
Solution Approach 1:
The device is divided into separate functional components: a stack structure for memory cell formation and a peripheral circuit structure for control functions. This segmentation allows each component to be optimized independently, with the peripheral circuit placed in a non-core region, thereby maintaining reliability while achieving high integration in the core region.
Solution Approach 2:
The invention transitions from planar two-dimensional integration to three-dimensional vertical stacking. Multiple memory cells are stacked vertically in the non-core region, enabling significant reduction in footprint area while maintaining operational reliability through proper separation from peripheral circuits.
2Productivity
If memory cells are stacked in a single layer on substrate, then integration is improved, but further integration improvement reaches a limit
Solution Approach 1:
The patent implements multi-layer vertical stacking of memory cells in the non-core region, transitioning from single-layer to three-dimensional stacking. This enables continuous integration improvement by adding more layers vertically rather than expanding horizontally or increasing single-layer density.
Solution Approach 2:
The device structure is segmented into core region (for peripheral circuits) and non-core region (for stacked memory cells). This spatial segmentation allows independent optimization of each region, enabling complex multi-layer structures without compromising peripheral circuit functionality.
3Stability of the object's composition
If peripheral circuit and stack structure are integrated, then device stability is improved, but manufacturing complexity increases
Solution Approach 1:
The device is manufactured by first forming the peripheral circuit in the core region, then separately forming the stack structure in the non-core region. This segmented manufacturing approach allows each component to be optimized and fabricated independently before final integration, reducing overall manufacturing complexity while achieving stable integrated device operation.
Data Source
AI summary
A semiconductor device may include: a peripheral circuit located on a substrate; a stack structure located over the peripheral circuit in a non-core region and including insulating layers and dummy layers that are alternately and repeatedly stacked; a channel pattern located on the stack structure; a transistor located on the channel pattern; a contact structure extending through the stack structure and electrically connecting the peripheral circuit to the channel pattern; a gate structure located over the peripheral circuit in a core region and including insulating layers and conductive layers that are alternately and repeatedly stacked; a first source pattern located on the gate structure; and a channel structure extending through the gate structure to contact the first source pattern.