3D Semiconductor Stack Layout for Dense MOSFET Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing demands for high performance, speed, and multifunctionality in semiconductor devices have led to challenges in improving the integration density and operational properties of planar metal oxide semiconductor field effect transistors (MOSFETs).
Innovation Solution
A semiconductor device is designed with a semiconductor stack body having different composition semiconductor layers and conductivity-type impurity regions, featuring recesses and through-holes, along with inactive gate structures, epitaxial patterns, and gap-fill insulating layers to enhance electrical properties and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If planar MOSFET size is reduced to increase integration density, then integration density is improved, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structure to three-dimensional FinFET structure with vertical fins extending from the substrate. This dimensional change increases the effective channel area without increasing planar footprint, thereby improving integration density while maintaining operational properties through enhanced gate control over the channel
Solution Approach 2:
The patent implements gate-all-around structure where the gate electrode completely surrounds the nanosheet channel in three dimensions. This nested configuration provides maximum gate control over the channel from all directions (top, bottom, and sidewalls), improving carrier modulation efficiency and operational reliability while maintaining compact device footprint
2Reliability
If FinFET with fin-shaped channel is developed to overcome planar MOSFET limitations, then operational properties are improved, but device complexity increases
Solution Approach 1:
The patent divides the channel into multiple discrete fin structures or nanosheets stacked vertically, each surrounded by its own gate. This segmentation allows independent optimization of each channel element and simplifies the manufacturing process by using repeated modular structures rather than a single complex continuous structure
Solution Approach 2:
The gate electrode structure serves multiple functions simultaneously: it provides electrical control over the channel, acts as a structural template for forming the fins or nanosheets, and functions as part of the interconnect system. This multi-functionality reduces the number of separate components needed, thereby reducing overall device complexity
3Reliability
If gate-all-around type field effect transistor with nanosheets is developed, then operational properties are improved, but manufacturing complexity increases
Solution Approach 1:
The patent forms the nanosheet channels and gate electrodes in a predetermined stacked configuration before final device assembly. The sacrificial layer method is used where temporary structures are formed first, then removed to create the final nanosheet geometry. This preliminary structuring simplifies subsequent manufacturing steps by establishing the complex three-dimensional architecture early in the process
Solution Approach 2:
The patent employs sacrificial layers as intermediary structures during manufacturing. These temporary layers are deposited and patterned to define the nanosheet geometry, then selectively removed to release the nanosheets and form the gate-all-around structure. This intermediary approach enables complex three-dimensional structures to be formed using standard planar processing techniques
Data Source
AI summary
A semiconductor device includes a semiconductor stack body having a first surface and a second surface, and including semiconductor layers having different compositions stacked therein, wherein the semiconductor stack body has a recess in the second surface and a through-hole penetrating through the semiconductor stack body; a plurality of inactive gate structures disposed on a second surface of the semiconductor stack body; a first conductivity-type epitaxial pattern disposed in the through-hole and connected to a first impurity region in the semiconductor stack body; a second conductivity-type epitaxial pattern disposed in the recess and connected to a second impurity region in the semiconductor stack body; a first contact connected to the first conductivity-type epitaxial pattern; and a second contact connected to the second conductivity-type epitaxial pattern.