High-Voltage Semiconductor Stack Structure Reducing On-Resistance
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Solution Overview
Problem
Traditional high-voltage semiconductor devices face increased on-resistance due to longer channel lengths, which also lead to larger device sizes and higher on-resistance in P-type devices compared to N-type devices, making them less efficient.
Innovation Solution
A high-voltage semiconductor device structure is developed with an epitaxial layer, a gate structure, source and drain regions, and a stack structure that includes a blocking layer, an insulating layer, and a conductive layer to decrease electric field density and on-resistance, utilizing epitaxial growth methods and chemical vapor deposition techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel length is increased to prevent punch-through between source and drain, then the device reliability is improved, but the device size and on-resistance increase
Solution Approach 1:
The patent introduces a vertical stack structure with multiple layers (blocking layer, insulating layer, conductive layer) stacked between the gate and drain, transitioning from a planar configuration to a three-dimensional vertical architecture. This dimensional change allows the device to achieve punch-through prevention through vertical field control rather than relying solely on increased horizontal channel length, thereby reducing chip area while maintaining reliability
2Reliability
If the channel length is increased to prevent punch-through between source and drain, then the device reliability is improved, but the on-resistance increases
Solution Approach 1:
The vertical stack structure enables control of the electric field in the vertical dimension, allowing punch-through prevention without proportionally increasing the horizontal channel length. This reduces the resistive path and minimizes on-resistance losses while achieving the required reliability
3Reliability
If the channel length is increased to prevent punch-through, then the device reliability is improved, but the device complexity increases
Solution Approach 1:
The patent segments the region between gate and drain into distinct functional layers (blocking layer, insulating layer, conductive layer), each performing a specific function in managing the electric field. This segmentation allows for optimized control of punch-through prevention while maintaining manageable device complexity through modular layer design
Solution Approach 2:
The stack structure employs composite materials with different electrical properties (blocking, insulating, and conductive layers) to create a multi-functional structure that addresses punch-through prevention through material diversity rather than structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure effectively decreases the on-resistance of high-voltage semiconductor devices by reducing electric field density in the channel, improving device efficiency and addressing the disparity between P-type and N-type devices.
Implementation Method 1
the stack structure includes: a blocking layer; an insulating layer disposed over the blocking layer; and a conductive layer disposed over the insulating layer and electrically connected to the source region or the gate structure
Data Source
AI summary
The present disclosure provides a high-voltage semiconductor device, including: a substrate; an epitaxial layer disposed over the substrate and having a first conductive type; a gate structure disposed over the epitaxial layer; a source region and a drain region disposed in the epitaxial layer at opposite sides of the gate structure respectively; and a stack structure disposed between the gate structure and the drain region, wherein the stack structure includes: a blocking layer; an insulating layer disposed over the blocking layer; and a conductive layer disposed over the insulating layer and electrically connected the source region or the gate structure. The present disclosure also provides a method for manufacturing the high-voltage semiconductor device.