Stepped Semiconductor Stack Etching With Passivation Planarization
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Solution Overview
Problem
The integration of semiconductor devices is limited by the area occupied by unit memory cells, and existing three-dimensional structures face challenges in maintaining a stable and reliable operational structure due to uneven surfaces and increased area issues during manufacturing.
Innovation Solution
A method of manufacturing a semiconductor device involving the formation of stacked structures with stepped surfaces, where a passivation layer is used as an etching barrier to prevent uneven surfaces and maintain a flat profile, thereby controlling the area and enhancing structural stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional stacked structures are formed to improve integration, then memory cell density increases, but uneven surfaces and area expansion occur during manufacturing
Solution Approach 1:
The manufacturing process is segmented into multiple etching stages with intermediate planarization steps. The stack structure is divided into multiple levels, and the patterning process is broken down into sequential steps that address each level independently, preventing area expansion at any single stage.
Solution Approach 2:
Planarization layers are applied in advance before subsequent etching operations. The uneven surfaces are预先 flattened using conformal deposition and etch-back processes, ensuring that the foundation for the next manufacturing step is already planarized, thus preventing area expansion in future steps.
2Ease of manufacture
If conventional etching processes are used on stacked structures, then manufacturing is simpler, but uneven surfaces are created that reduce reliability
Solution Approach 1:
Planarization layers are deposited in advance before subsequent etching operations. The uneven surfaces are预先 flattened using conformal deposition and etch-back processes, ensuring that the foundation for the next manufacturing step is already planarized, thus preventing area expansion in future steps.
Solution Approach 2:
A planarization layer acts as an intermediary between the uneven stack structure and the subsequent manufacturing processes. This intermediate layer provides a flat working surface while the underlying stack structure remains intact, allowing conventional manufacturing tools to operate effectively without directly encountering the uneven surfaces.
3Manufacturing precision
If multiple etching steps are performed without planarization, then manufacturing precision is lower, but process complexity increases
Solution Approach 1:
The manufacturing process is segmented into multiple etching stages with intermediate planarization steps. The stack structure is divided into multiple levels, and the patterning process is broken down into sequential steps that address each level independently, preventing area expansion at any single stage.
Solution Approach 2:
A planarization layer acts as an intermediary between the uneven stack structure and the subsequent manufacturing processes. This intermediate layer provides a flat working surface while the underlying stack structure remains intact, allowing conventional manufacturing tools to operate effectively without directly encountering the uneven surfaces.
Data Source
AI summary
A method of manufacturing a semiconductor device is provided. The method may include forming a stack, forming a preliminary stepped structure by patterning the stack, forming a first stepped structure, a second stepped structure, and an opening located between the first stepped structure and the second stepped structure by etching the preliminary stepped structure, forming a passivation layer that fills the opening and covers the first stepped structure, and forming a third stepped structure by etching the second stepped structure using the passivation layer as an etching barrier.