Semiconductor Layer Stack With Liner-Protected Sacrificial Etching
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Solution Overview
Problem
Current semiconductor structures face challenges in dislocation formation, stringent etch selectivity requirements, and limited freedom in choosing layer materials, which hinder the development of high-quality complementary FETs and other horizontal channel FET devices.
Innovation Solution
A method involving a layer stack with alternating sacrificial layers of different materials, protected by liner layers and inner spacers, allows for selective etching and dielectric filling, reducing lattice mismatch and etch selectivity, thereby minimizing dislocations and enabling a high degree of design freedom.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If alternating sacrificial layers of different materials are used, then freedom in choosing layer materials is improved, but etch selectivity requirements become more stringent
Solution Approach 1:
Liner layers are introduced as intermediary protective layers between alternating sacrificial layers of different materials. These liner layers prevent direct interaction between etchants and adjacent sacrificial layers with different etch rates, thereby reducing the stringency of etch selectivity requirements while maintaining freedom in material selection.
Solution Approach 2:
The structure is segmented into alternating sacrificial layers and liner layers, where each sacrificial layer can be independently optimized for specific materials while liner layers provide protective segmentation. This segmentation allows different materials to be used without requiring high selectivity between them, as the liner layers act as barriers during etching processes.
2Reliability
If sacrificial layers are removed by selective etching, then device structure is improved, but dislocation formation increases
Solution Approach 1:
The etching process parameters are changed by introducing liner layers that modify the etching environment. The liner layers alter the etch front propagation and stress distribution during selective removal of sacrificial layers, thereby reducing dislocation formation while achieving the desired device structure.
Solution Approach 2:
Liner layers are deposited beforehand on sacrificial layers to cushion and protect the underlying structure during selective etching. This prior protective layer prevents sudden stress changes and dislocation formation that would otherwise occur during the removal of sacrificial layers.
3Reliability
If liner layers and inner spacers are added, then protection of sacrificial layers is improved, but device complexity increases
Solution Approach 1:
Liner layers are designed to perform multiple functions simultaneously: they protect sacrificial layers during etching, serve as etch barriers, and can act as adhesion layers. This multi-functionality reduces the need for additional separate protective structures, thereby limiting the increase in device complexity while improving protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method results in a semiconductor structure with reduced dislocations, improved device performance, and enhanced freedom in choosing layer materials, facilitating further device scaling and strain distribution.
Implementation Method 1
forming recesses in the layer stack by laterally etching back the end surfaces of the first sacrificial layers from opposite ends of the layer stack, by selective etching; removing the at least one second sacrificial layer of the second sub-stack by etching, thereby forming at least one first cavity
Data Source
Figure 1a~1c
Figure 2a~3b
Figure 4a~5b
AI summary
The present invention provides a method for forming a semiconductor structure (100), the method comprising: forming a layer stack (110) on a substrate (102), the layer stack (110) comprising: a first sub-stack; a second sub-stack (130) on the first sub-stack (120) and comprising a plurality of sacrificial layers alternating between first and second sacrificial layers (132a, 132b), wherein neighboring first and second sacrificial layers (132a, 132b) of the second sub-stack (130) are separated by a liner layer (133); a third sub-stack (140) on the second sub-stack (130); forming recesses (160) in the layer stack; forming inner spacers (162) in the recesses (160); removing the at least one second sacrificial layer (132b) of the second sub-stack (130) by etching, thereby forming at least one first cavity (135); and filling the at least one first cavity (135) with dielectric material thereby forming at least one dielectric layer (136).