Semiconductor Stack Package Side-by-Side Chip Layout
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Solution Overview
Problem
Current semiconductor stack packages face challenges in achieving compact sizes and efficient electrical coupling while maintaining a reduced area for bonding pads, especially when multiple semiconductor chips are disposed side-by-side on a single plane, leading to increased space requirements and potential electrical shortages from intersecting bonding wires.
Innovation Solution
The semiconductor stack package design includes a printed circuit board with strategically positioned command/address and data input/output bonding pads, where semiconductor chips are spaced apart and electrically coupled using bonding wires that do not pass through the PCB, allowing for a compact layout and reduced area usage by eliminating the need for additional CA bonding pads between chips, and utilizing insulation layers to prevent wire sweep phenomena during molding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are disposed side-by-side on a single plane, then the package capacity is increased, but the area occupied by bonding pads increases
Solution Approach 1:
Multiple semiconductor chips are disposed side-by-side on a single plane of the package substrate, sharing common bonding pad structures. The bonding pads are arranged to serve multiple chips simultaneously, reducing the total area required compared to traditional vertical stacking where each chip requires dedicated bonding pads.
Solution Approach 2:
The patent transitions from vertical stacking (z-dimension) to horizontal arrangement (x-y plane) of semiconductor chips. This dimensional change allows chips to be disposed side-by-side, utilizing the planar area of the package substrate more efficiently and reducing the overall package height while maintaining high capacity.
2Reliability
If bonding wires are used to electrically couple chips, then electrical connectivity is achieved, but wire intersections cause electrical shortages
Solution Approach 1:
Insulation layers are selectively positioned at specific locations where bonding wires may intersect or come into close proximity. These local insulation structures prevent electrical shorts only where needed, rather than requiring insulation throughout the entire package, thus maintaining electrical connectivity while preventing harmful wire sweep phenomena.
Solution Approach 2:
Insulation layers act as intermediary structures between bonding wires that traverse different regions of the package. These insulation layers mediate potential electrical conflicts by providing physical separation and electrical isolation, allowing wires to cross without causing shorts while maintaining the overall electrical connectivity of the system.
3Area of stationary object
If chips are closely spaced to reduce area, then compactness is improved, but wire routing becomes complex
Solution Approach 1:
The package is segmented into distinct regions with dedicated bonding pad areas and chip disposal zones. Bonding wires are routed through defined pathways that avoid intersections, and insulation layers are placed at predetermined locations to manage wire routing complexity. This segmentation allows compact chip spacing while maintaining manageable wire routing.
Data Source
AI summary
A semiconductor stack package includes a printed circuit board (PCB), a first semiconductor chip, and a second semiconductor chip. The first and second semiconductor chips are disposed side-by-side on a first surface of the PCB to be spaced apart from each other. Each of the first and second semiconductor chips includes a command/address (CA) chip pad and a data input/output (DQ) chip pad. The CA chip pad of the first semiconductor chip is electrically coupled to the CA chip pad of the second semiconductor chip through a CA bonding wire.