Semiconductor Stack Sidewall Curvature for Integration Density
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Solution Overview
Problem
Three-dimensional semiconductor memory devices face challenges in increasing integration density while maintaining structural stability, as reducing memory cell layer thickness can lead to cell dissolution and collapse, and existing technologies struggle to reduce manufacturing costs while maintaining reliability.
Innovation Solution
A semiconductor device design featuring a stack with alternately stacked gate electrodes and insulating layers, including recessed and protruding portions on the sidewalls, which enhances structural stability and allows for effective deposition of metal layers without seams or voids, thereby preventing cell dissolution and improving integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cell layers is increased to increase integration density, then integration density is improved, but the stack may collapse or fall due to reduced structural stability
Solution Approach 1:
The sidewall of the stack is designed with a curved profile featuring recessed and protruding portions rather than a straight vertical wall. This curvature provides mechanical interlocking between adjacent memory cell layers, preventing stack collapse while enabling increased integration density through higher layer counts
2Stability of the object's composition
If the thickness of each memory cell layer is reduced to prevent stack collapse, then structural stability is improved, but cell dissolution phenomenon occurs
Solution Approach 1:
The curved sidewall profile with recessed and protruding portions creates mechanical interlocking that distributes stress across multiple layers. This allows each layer to maintain sufficient thickness for reliability while the overall stack achieves structural stability through the interlocking geometry
3Ease of manufacture
If conventional planar structures are used, then manufacturing process is simpler, but integration density is limited by fine pattern forming technology
Solution Approach 1:
The invention transitions from two-dimensional planar memory structures to three-dimensional vertically stacked structures. Multiple memory cell layers are stacked in the vertical direction, enabling integration density improvement without requiring proportionally finer lateral patterning, thus avoiding the need for extremely expensive fine pattern forming equipment
Data Source
AI summary
A semiconductor device includes a substrate, a stack, and channel structures penetrating the stack. The stack includes gate electrodes and insulating layers alternately and repeatedly stacked on the substrate, and extending in a first direction. The channel structures in a first row are spaced apart from each other in the first direction. The stack includes a first sidewall that includes first recessed portions and first protruding portions. Each of first recessed portions is defined by an adjacent pair of the first recessed portions. Each of the first recessed portions has a shape recessed toward a first region of the stack between an adjacent pair of the channel structures of the first row. Each of the first recessed portions has a width that decreases in a direction toward the first region when measured along the first direction.