Semiconductor Stack Structure with Slit Insulating Patterns
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Solution Overview
Problem
Three-dimensional nonvolatile memory devices face challenges in improving operational reliability due to limitations in their stacked structures and manufacturing methods, particularly in maintaining stable and efficient integration of memory cells.
Innovation Solution
A semiconductor device with a stack structure featuring alternately stacked sacrificial and insulating layers, and conductive and insulating layers, including a first slit insulating layer and slit insulating patterns that penetrate the stack structure, allowing for the replacement of sacrificial layers with conductive layers and a heat treatment process to enhance structural stability and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional nonvolatile memory devices use stacked structures with alternately stacked interlayer insulating layers and gate electrodes, then the degree of integration is improved, but the operational reliability deteriorates due to structural instability and manufacturing difficulties
Solution Approach 1:
The stack structure is divided into a first region with sacrificial layers and insulating layers, and a second region with conductive layers and insulating layers. This segmentation allows different regions to serve different functions: the first region maintains structural stability during manufacturing, while the second region provides the necessary electrical connectivity, thereby resolving the contradiction between integration and reliability.
Solution Approach 2:
Sacrificial layers are formed in advance in the first region before the final conductive structure is completed. These preliminary sacrificial structures provide structural support during the manufacturing process and are later replaced with conductive layers, enabling both high integration and operational reliability.
2Productivity
If channel layers penetrate through alternately stacked interlayer insulating layers and gate electrodes, then memory cells can be vertically stacked, but manufacturing precision deteriorates due to the complexity of forming precise penetrations through multiple layers
Solution Approach 1:
Sacrificial layers act as intermediary structures that facilitate the formation of channel layers. The sacrificial layers are formed first, providing a template and structural support, and then channel layers are formed to penetrate through the stack. This intermediary approach simplifies the manufacturing process and improves precision compared to directly forming penetrations through all layers.
Solution Approach 2:
The sacrificial layers are formed in advance to define the positions where channel layers will penetrate. This preliminary structuring provides a guide for subsequent processing steps, ensuring precise penetration of channel layers through the multi-layer stack without requiring complex direct patterning.
3Adaptability or versatility
If sacrificial layers are replaced with conductive layers, then the device functionality is improved, but the structural stability deteriorates during the replacement process
Solution Approach 1:
The first slit insulating layer is formed in advance to define the boundaries of the first region where sacrificial layers will be replaced. This preliminary insulation structure maintains structural stability during the replacement process by providing a stable framework that prevents collapse or misalignment when sacrificial layers are removed and conductive layers are deposited.
Solution Approach 2:
The replacement of sacrificial layers with conductive layers is performed locally in the first region, bounded by the first slit insulating layer. This localized approach allows the replacement to occur in a controlled manner, maintaining structural stability in other regions while achieving the necessary functionality in the target region.
4Adaptability or versatility
If multiple slit insulating patterns are formed to replace sacrificial layers, then the conductivity is improved, but the device complexity increases
Solution Approach 1:
Multiple slit insulating patterns are merged into a unified structure in the second region, where conductive layers and insulating layers are alternately stacked. This merging approach achieves the necessary conductivity through the combined effect of multiple patterns while presenting a more simplified and integrated structure, reducing the perceived complexity compared to having separate, independent patterns.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves the structural stability and operational reliability of three-dimensional semiconductor devices by ensuring proper integration and conductivity, simplifying the manufacturing process and enhancing the reliability of memory cells.
Implementation Method 1
performing a heat treatment process, wherein the first slit insulating layer and the slit insulating patterns are shrunk with different heights
Implementation Method 2
the first slit insulating layer and the slit insulating patterns are shrunk with different heights
Data Source
AI summary
A semiconductor device includes a stack structure located on a substrate and includes a first region, in which sacrificial layers and insulating layers are alternately stacked, and a second region, in which conductive layers and insulating layers are alternately stacked. The stack structure also includes a first slit insulating layer located at a boundary between the first region and the second region, wherein the first slit insulating layer penetrates the stack structure and extends in one direction. The stack structure further includes a plurality of slit insulating patterns located in the second region, wherein the plurality of slit insulating patterns penetrate the stack structure and are arranged along the one direction. At least one conductive layer among the conductive layers is bent between the first slit insulating layer and the slit insulating patterns.