Semiconductor Package Stack With Vertical Interconnect Alignment
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Solution Overview
Problem
The semiconductor industry faces challenges in integrating complex functionalities into smaller devices due to space constraints and routing traces on printed circuit boards, necessitating an improved semiconductor package design for enhanced integration and reduced wiring complexity.
Innovation Solution
A semiconductor package stack is developed, featuring a base substrate with conductive patterns, anisotropic conductive film, and vertically extending semiconductor packages and substrates with exposed conductive patterns, allowing for electrical connections via the anisotropic conductive film, which reduces space occupation and improves integration by enabling high-density, miniaturized designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional planar PCB routing is used, then trace routing is straightforward, but space occupation increases and integration density decreases
Solution Approach 1:
The patent transitions from traditional planar (2D) PCB routing to a three-dimensional vertical stacking architecture. Conductive patterns are arranged in multiple layers vertically, with through-silicon vias and interlayer connections enabling electrical pathways in the Z-dimension. This dimensional transition reduces the horizontal footprint and allows higher integration density while maintaining manageable wiring complexity through standardized vertical interconnection processes.
2Productivity
If vertical stacking is implemented, then integration density improves and space occupation reduces, but alignment precision requirements increase
Solution Approach 1:
The patent introduces alignment marks, fiducial features, and intermediary alignment layers between stacking stages. These intermediary elements serve as reference points that facilitate precise registration of conductive patterns across multiple layers. The alignment marks are embedded in intermediate layers or on substrate surfaces, providing visual or mechanical references that reduce the cumulative alignment error in vertical stacking processes.
3Adaptability or versatility
If more conductive patterns are added for enhanced functionality, then device performance improves, but wiring complexity and routing difficulty increase
Solution Approach 1:
The patent segments the wiring design into modular functional blocks, each with dedicated conductive pattern sets. Different functionality modules (e.g., power delivery, signal transmission, ground planes) are implemented as separate conductive layers or pattern groups. This segmentation allows independent optimization of each functional wiring system and simplifies the overall design complexity by breaking down the monolithic wiring challenge into manageable, reusable modules.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables efficient electrical connections and improved integration by allowing vertical electrical paths without horizontal conductive paths, thus enhancing the packing density and performance of semiconductor packages.
Implementation Method 1
an anisotropic conductive film formed on the front surface of the base substrate
Data Source
AI summary
A semiconductor package stack comprises: a base substrate having one or more sets of base conductive patterns on its front surface; an anisotropic conductive film formed on the front surface of the base substrate; one or more semiconductor packages disposed on the base substrate via the anisotropic conductive film, wherein each of the one or more semiconductor packages comprises package interconnect structures which have package conductive patterns exposed from a lateral surface of the semiconductor package; and wherein the package conductive patterns are aligned with base conductive patterns; and a vertical substrate disposed on the base substrate via the anisotropic conductive film, wherein the vertical substrate comprises vertical interconnect structures which have vertical conductive patterns exposed from a lateral surface of the vertical substrate; and wherein the vertical conductive patterns are aligned with base conductive patterns.