Semiconductor Stack Structure with Vertical Conductive Plugs
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity and reliability, particularly in achieving high-capacity data storage systems.
Innovation Solution
A semiconductor device design featuring a substrate with a stack structure of interlayer insulating layers and gate electrodes, including separation regions and vertical structures that extend through the stack, enhancing data storage capacity and reliability by optimizing the arrangement of channel structures and gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally arranged memory cells are used instead of two-dimensionally arranged memory cells, then data storage capacity is increased, but manufacturing complexity and reliability challenges arise
Solution Approach 1:
The semiconductor device is divided into multiple memory cell strings arranged in parallel, with each string containing multiple memory cells connected in series. This segmentation allows the complex three-dimensional structure to be manufactured through systematic formation of sacrificial structures, holes, and conductive plugs in discrete steps, reducing overall manufacturing complexity while maintaining high storage capacity.
Solution Approach 2:
The patent employs a nested structure where conductive plugs are formed within holes that are formed within sacrificial structures, creating a hierarchical arrangement. The first conductive plugs are positioned within first holes in first sacrificial structures, and second conductive plugs are positioned within second holes in second sacrificial structures. This nesting enables compact three-dimensional integration and increases storage capacity without proportionally increasing manufacturing complexity.
2Quantity of substance
If three-dimensionally arranged memory cells are used instead of two-dimensionally arranged memory cells, then data storage capacity is increased, but reliability issues occur
Solution Approach 1:
Sacrificial structures are formed in advance as part of the manufacturing process, serving as temporary placeholders that are later removed to create holes for conductive plugs. This preliminary action ensures precise positioning and proper formation of the three-dimensional memory cell structure, improving device reliability by preventing misalignment and structural defects.
Solution Approach 2:
The sacrificial structures act as intermediary elements during manufacturing, facilitating the formation of holes and conductive plugs before being removed. These intermediary structures enable precise three-dimensional integration and proper electrical connections, thereby improving the reliability of the final semiconductor device while maintaining high storage capacity.
3Productivity
If vertical structures extend through separation regions, then integration density is increased, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies different structural characteristics to different regions of the semiconductor device. Separation regions contain vertical structures that extend through the stack structure, while cell regions contain channel structures with memory cells. This local differentiation allows high integration density in cell regions while using separation regions for electrical isolation, reducing the overall precision requirements for etching across the entire device.
Solution Approach 2:
The device is segmented into distinct cell regions and separation regions, with each region having specific structural and functional characteristics. This segmentation allows the manufacturing process to address different precision requirements in different areas, improving overall integration density while managing etching precision challenges through localized structural design.
Data Source
AI summary
A semiconductor device includes a substrate; a stack structure on the substrate and including an alternating stack of interlayer insulating layers and gate electrodes; first and second separation regions each extending through the stack structure and extending in a first direction; a first upper separation region between the first and second separation regions and extending through a portion of the stack structure; a plurality of channel structures between the first and second separation regions and extending through the stack structure; and a plurality of first vertical structures each extending through a particular one of the first and second separation regions. Each of the first and second separation regions has a first width in a second direction that is perpendicular to the first direction. Each first vertical structure has a second width in the second direction, the second width being greater than the first width.