Semiconductor Apparatus Stacked Bank Structure Read-While-Write
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Solution Overview
Problem
Conventional phase-change random access memory (PRAM) exhibits low data processing speed and increased chip area due to the need for independent operations of multiple banks during read-while-write operations, leading to inefficiencies in write current usage and increased chip size.
Innovation Solution
A semiconductor apparatus with a stacked bank structure, featuring separate write and read global bit lines, a centralized write operation controller, and a verify sense amplifier to enable simultaneous read-while-write operations, reducing chip area and write current loss by separating write and read paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple banks are configured to perform independent operations for read-while-write, then data processing speed is improved, but chip area is increased due to duplicate components in each bank
Solution Approach 1:
The patent implements a shared write operation controller that serves multiple bank groups (first bank group and second bank group) simultaneously. This write operation controller is configured to control write operations for both bank groups, eliminating the need for separate write operation controllers in each bank group. This multi-functional approach enables read-while-write operations across different banks while significantly reducing the number of duplicate components, thereby improving data processing speed without proportionally increasing chip area.
2Adaptability or versatility
If each bank includes independent X-decoder, Y-decoder, and W/D & S/A block for independent operation, then read-while-write operation is enabled, but device complexity is increased
Solution Approach 1:
The patent employs a universal write operation controller that can control write operations across multiple bank groups. This single controller is designed to manage write operations for both the first bank group and second bank group, reducing the overall number of control components while maintaining the capability for independent read-while-write operations in each bank group.
Solution Approach 2:
The patent divides the memory system into separate bank groups (first bank group and second bank group) with shared control resources. By segmenting the banks while sharing the write operation controller, the system achieves independent operation capability for read-while-write while avoiding the complexity of fully independent control for each bank.
3Productivity
If banks are arranged to enable simultaneous read and write operations, then productivity is improved, but write current loss increases due to longer operation paths
Solution Approach 1:
The patent arranges bank groups in a spatial configuration where the write operation controller is positioned to minimize operation path length. By organizing the first bank group and second bank group around the central write operation controller, the patent reduces the physical distance current must travel during write operations, thereby reducing write current loss while maintaining the capability for simultaneous read and write operations across different banks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances data processing speed and reduces chip area by allowing simultaneous read and write operations across banks, minimizing write current loss and optimizing the operation path, thereby improving overall performance.
Implementation Method 1
generates a phase change between amorphous and crystalline structures of a phase change layer formed of chalcogenide through Joule heating caused by a current between a top electrode and a heating electrode serving as a heater
Implementation Method 2
generates a phase change between amorphous and crystalline structures of a phase change layer formed of chalcogenide
Data Source
AI summary
A semiconductor apparatus includes: a first bank group comprising a plurality of first banks; a second bank group comprising a plurality of second banks arranged adjacent to the first bank group; a write operation controller arranged between the first and second bank groups so as to be adjacent to the first and second bank groups, and configured to control write operations of the first and second bank groups; and a read operation controller arranged adjacent to any one of the first and second bank groups and configured to control read operations of the first and second bank groups.