Semiconductor Device Stacked Capacitive Circuit Area Reduction
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Solution Overview
Problem
The challenge in semiconductor devices is to reduce the circuit area of capacitive circuits while maintaining high capacitance and memory density, particularly in cross-point type memory cell arrays where achieving a metal-oxide-metal (MOM) structure is difficult without altering the standard structure.
Innovation Solution
The capacitive circuit is configured such that bit lines, memory cells, and word lines overlap each other in a line shape, forming a stacked structure that functions as part of an electrode in the MOM structure, allowing for high capacitance per unit area and reduced circuit area, using the same microfabrication processes as the memory cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional capacitive circuit structure is used, then the circuit area is large, but the capacitance per unit area is low
Solution Approach 1:
The patent transitions from a planar capacitive circuit structure to a three-dimensional stacked structure by overlapping bit lines, memory cells, and word lines vertically. This dimensional change allows multiple conductive layers to occupy the same footprint area, significantly increasing capacitance per unit area while reducing the overall circuit area required
2Reliability
If the standard cross-point memory cell array structure is altered to achieve MOM structure, then the capacitive circuit performance improves, but the manufacturing complexity increases
Solution Approach 1:
The patent makes the memory cell array structure serve dual functions: it maintains its original memory storage capability while simultaneously forming the capacitive circuit structure. The bit lines, memory cells, and word lines are configured to create overlapping electrode patterns that function as both memory elements and capacitor electrodes, eliminating the need for separate MOM structure fabrication processes
Solution Approach 2:
The patent merges the memory cell array structure with the capacitive circuit structure by using the same physical layers (bit lines, memory cells, word lines) to fulfill both memory and capacitive functions. This consolidation allows the formation of metal-oxide-metal capacitor structures without requiring additional fabrication steps or altering the standard cross-point memory architecture
Data Source
AI summary
A semiconductor device includes a plurality of first conductive lines in a first wiring layer, a plurality of second conductive lines in a second wiring layer, and a plurality of memory cells between the first and second conductive lines in a first direction in a first region. A plurality of third conductive lines in the first wiring layer, a plurality of fourth conductive lines in the second wiring, and a plurality of first memory lines are in a second region. The third conductive lines extends in a second direction and are spaced from each other in a third direction. The fourth conductive lines extend in the second direction and are spaced in the third direction. The first memory lines are between the third conductive lines and the fourth conductive lines in the first direction. The first memory lines comprise the same materials as the memory cells.