Semiconductor Device Stacked Chip Height Variation
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Solution Overview
Problem
The challenge in semiconductor devices is the increase in size due to the stacking of chips, which leads to a larger area for mounting in directions intersecting with the stacking direction, making it difficult to reduce the device size while maintaining efficient component placement.
Innovation Solution
The semiconductor device employs a configuration where the first and second stacked components, with varying thicknesses and bonding layers, are positioned to create a closer packing arrangement, utilizing a spacer and controller chip placement to minimize size while maintaining a predetermined distance between components, and using a recess on the sealing resin to reduce overall height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple chips are stacked on the substrate and arranged side by side, then the component placement efficiency is improved, but the device size increases in the direction intersecting with the stacking direction
Solution Approach 1:
The patent transitions from two-dimensional planar arrangement to three-dimensional stacked arrangement of chips. Multiple chips are arranged in vertical stacks on the substrate, utilizing the height dimension to increase component placement capacity without proportionally increasing the device footprint area.
Solution Approach 2:
The patent implements nested arrangement where chips of different types (first chips and second chips) are stacked vertically one on top of another, with each stack containing multiple chips. This nesting approach allows dense packing of components in the vertical direction while maintaining compact device dimensions.
2Area of stationary object
If chips are positioned closer together to reduce device size, then the device footprint is reduced, but interference between chips may occur
Solution Approach 1:
The patent applies different characteristics to different regions: spacer structures are positioned between specific chip stacks where interference risk exists, while other regions maintain direct chip-to-substrate contact. This localized intervention provides interference prevention only where necessary, optimizing both compactness and reliability.
Solution Approach 2:
Spacer structures serve as intermediary elements positioned between adjacent chip stacks. These spacers maintain appropriate spacing to prevent interference between chips while allowing the overall device footprint to remain compact. The spacers act as mediators that enable close packing without direct chip contact.
Data Source
AI summary
According to one embodiment, a semiconductor device includes a substrate, first stacked components, second stacked components, and a coating resin. The first stacked components include first chips and are stacked on a surface of the substrate. The second stacked components include second chips and are stacked on the surface. The coating resin covers the surface, the first stacked components, and the second stacked components. A first top surface of a second farthest one of the first chips away from the surface differs in position in a first direction from a second top surface of second farthest one of the second chips away from the surface.