Semiconductor Device Stacked Chips Internal Wiring Resistance
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Solution Overview
Problem
Wiring resistance and wiring inductance in printed circuit boards hinder the reduction of power consumption and performance enhancement in electronic circuits when connecting functional element chips.
Innovation Solution
A semiconductor device configuration that includes functional element chips, electric connection members, and wires bonded within a resin, where the wires overlap with the connection members in the thickness direction of the chips, eliminating the need for external wiring lines and reducing resistance and inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If functional element chips are electrically connected via wiring lines of a printed circuit board, then the chips can be interconnected to form electronic circuits, but wiring resistance and wiring inductance are generated which increase power consumption and reduce performance
Solution Approach 1:
The patent transitions from planar wiring connections to three-dimensional stacked connections. Multiple functional element chips are vertically stacked and electrically connected through conductive structures (conductor plates, wires, or conductive pillars) that extend through the stack, enabling direct inter-chip communication without lateral wiring paths. This vertical integration dramatically shortens current paths, reducing both resistance and inductance while improving power efficiency and performance.
Solution Approach 2:
The patent implements nested conductor structures where conductor plates are embedded within the chip stack, wires are positioned between chips, and conductive pillars extend through multiple layers. These conductive elements are nested within the resin encapsulation and between functional element chips, creating integrated connection paths that eliminate external wiring requirements and reduce parasitic effects.
2Reliability
If wiring lines are used to connect functional element chips, then electrical interconnection is achieved, but wiring inductance is generated which hampers performance enhancement
Solution Approach 1:
The patent employs vertical stacking architecture where functional element chips are arranged in multiple layers and connected through conductive structures extending in the thickness direction. This three-dimensional configuration replaces traditional planar wiring with direct vertical pathways, minimizing loop areas and reducing inductance. The stacked arrangement enables faster signal transmission and improved performance while maintaining connection stability.
Solution Approach 2:
The patent divides the electrical connection system into segmented conductive paths within each chip layer and between layers. Conductor plates, wires, and conductive pillars create discrete connection segments that are optimized for specific functions. This segmentation allows independent optimization of each connection path, reducing overall inductance while maintaining reliable electrical connectivity across the multi-chip structure.
Data Source
AI summary
A semiconductor device includes a plurality of functional element chips, an electric connection member joined to two of the functional element chips, a first wire and a resin configured to cover the functional element chips, the electric connection member and the first wire. One of the two functional element chips may be a first semiconductor chip having first and second major surface electrodes facing toward the same direction and a first rear surface electrode facing in a direction opposite to a direction in which the first major surface electrode faces. The electric connection member may be joined to the first major surface electrode. The first wire may be joined to the second major surface electrode. The first wire may include a portion overlapping with the electric connection member in a thickness direction of the first semiconductor chip.