Semiconductor Device Stacked Conductor Thermal Stress
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Solution Overview
Problem
The existing semiconductor memory devices with three-dimensional structures face issues of peeling and substrate warping due to thermal expansion mismatch between conductors and substrates, leading to stress-related manufacturing challenges and reliability concerns during downscaling.
Innovation Solution
A semiconductor device design incorporating a stacked conductor structure with a first layer of tungsten and a second layer of polysilicon, where the thermal expansion coefficient of the second layer is closer to that of the substrate, reducing compressive stress in the conductor and tensile stress in the substrate, thereby minimizing peeling and warping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single-layer conductor is filled into the slit to form a source line, then the electrical connection is achieved, but peeling of the stacked body and warp of the substrate occur due to thermal expansion mismatch and stress
Solution Approach 1:
The patent applies composite materials by forming a stacked conductor structure consisting of a first conductor layer and a second conductor layer with different thermal expansion coefficients. The first conductor layer has a thermal expansion coefficient closer to that of the stacked body, while the second conductor layer has a thermal expansion coefficient closer to that of the substrate. This composite structure distributes thermal stress more evenly, preventing peeling of the stacked body and warping of the substrate that would occur with a single-layer conductor.
Solution Approach 2:
The patent changes the physical parameter of thermal expansion coefficient by selecting different materials for the first and second conductor layers. The first conductor layer is made of a material with a thermal expansion coefficient matching the stacked body, and the second conductor layer is made of a material with a thermal expansion coefficient matching the substrate. This parameter matching reduces thermal stress and prevents structural defects during temperature variations in the manufacturing process.
2Volume of moving object
If conductor volume is reduced for downscaling, then device size is reduced, but stress relief becomes more critical and peeling may occur
Solution Approach 1:
The stacked conductor structure with two layers of different materials provides inherent stress relief capability. Even when the overall conductor volume is reduced for downscaling, the composite structure maintains stress distribution, preventing peeling and reliability issues that would be more pronounced in smaller devices with single-layer conductors.
Solution Approach 2:
By carefully selecting the thermal expansion coefficients of the conductor layer materials to match those of the stacked body and substrate, the patent minimizes thermal stress even in scaled-down devices. This parameter optimization ensures that stress relief is maintained despite the reduced conductor volume.
3Ease of manufacture
If thermal expansion coefficients are mismatched between conductor and substrate, then manufacturing is simplified, but substrate warping and manufacturing precision deteriorate
Solution Approach 1:
The stacked conductor structure with two layers of different materials provides inherent stress relief capability. Even when the overall conductor volume is reduced for downscaling, the composite structure maintains stress distribution, preventing peeling and reliability issues that would be more pronounced in smaller devices with single-layer conductors.
Solution Approach 2:
By carefully selecting the thermal expansion coefficients of the conductor layer materials to match those of the stacked body and substrate, the patent minimizes thermal stress even in scaled-down devices. This parameter optimization ensures that stress relief is maintained despite the reduced conductor volume.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively relaxes stress in both the conductor and substrate, enhancing manufacturing precision and reliability by maintaining the stacked structure and ensuring uniform resistance across the memory cell array, facilitating the downscaling of memory devices.
Implementation Method 1
the thermal expansion coefficient of the second layer is closer to that of the substrate, reducing compressive stress in the conductor and tensile stress in the substrate
Data Source
AI summary
According to one embodiment, a semiconductor device includes a substrate; a stacked body; a columnar portion; a plate portion; and a sidewall insulating film. The thermal expansion coefficient of the substrate is α1. The stacked body includes a plurality of electrode layers and a memory cell array. The columnar portion includes a semiconductor body and a charge storage film. The plate portion includes a first layer and a second layer. The thermal expansion coefficient of the first layer is the α2 being different from the α1. The thermal expansion coefficient of the second layer is the α3 being different from the α2. The value of the α3 is in a direction from the value of the α2 toward the value of the α1. The second layer faces the major surface of the substrate continuously in the memory cell array.