Semiconductor Package With Substrate Window For Stacked Die

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Solution Overview

Problem

Current semiconductor manufacturing techniques face challenges in producing packages with multiple integrated semiconductor dies over a single substrate, limited by space constraints and the need for spacers or dummy layers, which increases costs and reduces efficiency.

Innovation Solution

A method involving a substrate with a window, where semiconductor devices are mounted and interconnected using adhesives and wirebonds, allowing for stacking and electrical connections through the window, and encapsulated using a two-step molding process to reduce material costs and process steps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If spacers or dummy layers are used to control the configuration of semiconductor die, then the positioning precision is improved, but the device complexity and manufacturing cost increase

Engineering Contradiction:
Improvepositioning precisionVSAvoidstructure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent removes spacers and dummy layers from the packaging structure, using only the essential substrate with mounting surfaces. This extraction of non-essential elements reduces structural complexity while maintaining the ability to precisely position multiple semiconductor die through the substrate's mounting surfaces and bonding processes.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The substrate serves multiple functions: it provides mechanical support, defines the configuration of stacked die, enables electrical connections, and eliminates the need for separate spacer or dummy layer components. This multi-functionality reduces overall device complexity while maintaining manufacturing precision.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If more semiconductor die are integrated over a single substrate, then the productivity is improved, but the manufacturing precision deteriorates due to space limitations

Engineering Contradiction:
Improveintegration densityVSAvoidpositioning precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent transitions from planar integration to three-dimensional stacked integration of semiconductor die. By stacking die vertically over the substrate rather than arranging them side-by-side in two dimensions, the system achieves higher integration density while maintaining positioning precision through controlled bonding processes and substrate mounting surfaces.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Multiple semiconductor die are nested in a stacked configuration over the substrate, with each die positioned and bonded to the substrate or to other die. This nesting approach allows high integration density while maintaining precise positioning through the bonding process and substrate structure.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Loss of time

If a window is provided in the substrate for wirebond passage, then the manufacturing time is reduced, but the structural strength is weakened

Engineering Contradiction:
Improvemanufacturing timeVSAvoidstructural strength
Core Design Contradiction:
Loss of timeVSStrength

Solution Approach 1:

The patent extracts the wirebond passage function from the substrate body by creating a window or opening. This allows wirebonds to pass directly through the substrate without requiring complex routing or drilling operations, reducing manufacturing time while the window is designed to maintain adequate structural strength.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The substrate has different structural properties in different regions: the window area is optimized for wirebond passage with minimal material removal, while surrounding areas maintain full thickness and strength. This local differentiation allows the substrate to provide both easy wirebond access and adequate structural strength.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the integration of multiple semiconductor dies over a single substrate, reducing manufacturing time and costs while improving circuit performance by minimizing signal propagation distance and capacitance.

Implementation Method 1

mounting first and second semiconductor devices to a top surface of the substrate on either side of the window using an adhesive

Methodology Applied
Scientific EffectAdhesion: Adhesive

Implementation Method 2

forming a wirebond between the third semiconductor device and a contact pad formed over a bottom surface of the substrate opposite the top surface of the substrate. The wirebond passes through the window of the substrate

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 3

depositing an encapsulant over the first, second, and third semiconductor devices

Methodology Applied
Scientific EffectEncapsulation:

Data Source

PatentUS8354742B2Method and apparatus for a package having multiple stacked die
Publication Date: 2013.01.15 STATS CHIPPAC LTD
  • US8354742B2 patent drawing
  • US8354742B2 patent drawing
  • US8354742B2 patent drawing

AI summary

A method of manufacturing a semiconductor package involves providing a substrate having a window. The substrate may include a leadframe having half-etched leads. First and second semiconductor devices are mounted to a top surface of the substrate on either side of the window using an adhesive. A third semiconductor device is mounted to the first and second semiconductor devices using an adhesive. The third semiconductor device is disposed over the window of the substrate. A wirebond or other electrical interconnect is formed between the third semiconductor device and a contact pad formed over a bottom surface of the substrate opposite the top surface of the substrate. The wirebond or other electrical interconnect passes through the window of the substrate. An encapsulant is deposited over the first, second, and third semiconductor devices.