Semiconductor Device Stacked Gate Structure Integration Density
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Solution Overview
Problem
The integration density of semiconductor devices is limited by the area occupied by unit memory cells, and existing technologies face challenges in enhancing operational reliability, particularly as two-dimensional memory cell formation reaches its limits, necessitating innovative three-dimensional stacking solutions.
Innovation Solution
A semiconductor device with a stacked gate structure, including block and local word lines, a pass transistor with a U-shaped channel layer, and an interconnection structure that connects local and gate lines, along with a manufacturing method involving trench formation, gate insulating layer deposition, and channel layer formation to enhance integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional memory cell formation is used, then manufacturing process is simple, but integration density reaches its limit
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional stacked structure, forming memory cells in multiple layers vertically. This dimensional change enables significantly higher integration density by utilizing the vertical space, allowing more memory cells to be packed into a smaller footprint area.
Solution Approach 2:
The patent implements nested word line structures where global word lines and local word lines are stacked in layers. The global word lines extend across multiple memory blocks while local word lines connect to specific blocks, creating a nested hierarchical structure that efficiently manages connections in three-dimensional space.
2Quantity of substance
If pass transistor area is reduced, then integration density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the word line structure into global word lines and local word lines, with pass transistors positioned at intersections. This segmentation allows for modular design and independent optimization of different transistor regions, facilitating better manufacturing control while maintaining high integration density.
Solution Approach 2:
The patent applies different structural characteristics to different regions of the pass transistor. The channel layer has a U-shape with specific width and depth dimensions optimized for local current flow requirements, while source and drain regions are configured with specific doping concentrations. This local optimization enables precise control of electrical characteristics despite area reduction.
3Quantity of substance
If three-dimensional stacking is implemented, then integration density improves, but operational reliability challenges increase
Solution Approach 1:
The patent designs the stacked gate structure and word line connections to ensure uniform voltage distribution across all memory blocks. Global word lines provide consistent voltage to multiple blocks simultaneously, and local word lines ensure proper voltage application to individual blocks, maintaining operational reliability despite three-dimensional stacking.
Solution Approach 2:
The patent optimizes physical parameters such as the U-shaped channel layer dimensions, doping concentrations, and insulating layer thicknesses to control electrical characteristics. By carefully adjusting these parameters, the patent maintains stable current flow and reduces leakage currents, thereby ensuring operational reliability in the three-dimensional structure.
4Power
If cell current is increased, then device performance improves, but leakage current increases
Solution Approach 1:
The patent applies different doping concentrations and structural configurations to source, drain, and channel regions of the pass transistor. The U-shaped channel layer provides a controlled current path with optimized width and depth, while source and drain regions are doped to specific concentrations to enable efficient carrier injection and collection. This local optimization increases cell current while managing leakage.
Solution Approach 2:
The patent uses composite insulating structures including gate insulating layers, word line insulating layers, and contact hole insulating layers with different dielectric properties. These composite insulating structures provide electrical isolation while maintaining mechanical stability, enabling controlled current flow through the channel while blocking leakage paths.
Data Source
AI summary
A semiconductor device including a first block word line, and a first channel layer located in the first block word line. the semiconductor device including a source pad connected to the first channel layer and located on the first block word line, and a first drain pad connected to the first channel layer and located on the first block word line. The semiconductor device including a global word line connected to the source pad, and a first local word line connected to the first drain pad.