Semiconductor Device Stacked on Flat Lead Frame
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Solution Overview
Problem
Conventional semiconductor devices with stacked semiconductor elements face increased manufacturing costs and size limitations due to depression processes and inefficient resin sealing, especially when stacking on lead frames or wiring boards.
Innovation Solution
A semiconductor device design featuring a flat lead frame with stacked semiconductor elements connected via adhesive layers and metal wires, where the ends of the metal wires are embedded in the adhesive layers to prevent short circuits and allow for efficient resin sealing, enabling the stacking of multiple elements on one surface without depressing the lead frame.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a depression process is applied to the lead frame to increase the number of mountable semiconductor elements, then the mounting density is improved, but the manufacturing cost increases and the element size is limited
Solution Approach 1:
The patent transitions from a two-dimensional planar mounting arrangement to a three-dimensional stacked arrangement by mounting semiconductor elements on both the upper and lower surfaces of the lead frame. This vertical stacking approach increases the number of mountable elements without requiring a depression process, thereby maintaining manufacturing simplicity while achieving higher mounting density.
2Quantity of substance
If a depression process is applied to the lead frame to increase the number of mountable semiconductor elements, then the mounting density is improved, but the element size is limited
Solution Approach 1:
By utilizing the vertical dimension through stacking elements on both surfaces of the lead frame, the patent allows larger elements to be mounted on each surface without compromising the number of mountable elements. The flat upper surface provides sufficient area for larger elements, eliminating the size constraints imposed by depression processes.
3Quantity of substance
If semiconductor elements are stacked on both surfaces of the lead frame, then the mounting density is improved, but the resin sealing performance deteriorates due to pad arrangement and lead frame shape
Solution Approach 1:
The patent employs asymmetric pad arrangements on the semiconductor elements, with electrode pads concentrated on one surface rather than distributed on both surfaces. This asymmetric configuration, combined with the lead frame structure, creates favorable conditions for resin flow and sealing during the molding process, thereby maintaining high sealing performance while enabling dual-surface mounting.
4Reliability
If semiconductor elements are stacked in a stepped manner to expose electrode pads, then the electrical connection is improved, but the area occupied on the wiring board increases
Solution Approach 1:
The patent resolves the area occupation issue by transitioning from horizontal expansion to vertical stacking. Semiconductor elements are stacked in the vertical direction on both surfaces of the lead frame, allowing multiple elements to share the same footprint area. This three-dimensional arrangement maintains electrical connectivity through wire bonding while minimizing the area occupied on the wiring board.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces manufacturing costs, increases the size of mountable semiconductor elements, and enhances sealing reliability while maintaining a compact package size, improving the reliability and capacity of semiconductor devices.
Implementation Method 1
a first semiconductor element having a first electrode forming surface on which first electrode pads are formed, the first semiconductor element being adhered to a lower surface of the lead frame via a first adhesive layer
Implementation Method 2
first metal wires electrically connecting the inner leads and the first electrode pads; second metal wires electrically connecting the inner leads and the second electrode pads
Implementation Method 3
a resin sealer sealing the first and second semiconductor elements together with the first and second metal wires
Data Source
AI summary
A semiconductor device includes a lead frame having an element support and a lead portion. The lead frame has an area from the element support to inner leads of the lead portion, which is formed flat. First and second semiconductor elements are stacked in order on a lower surface of the lead frame. Electrode pads of the first semiconductor element are connected to the inner leads via first metal wires. Ends of the first metal wires, which are connected to the first semiconductor element, are embedded in the second adhesive layer of the second semiconductor element.