Semiconductor Device With Stacked Memory And Universal Operation Circuit
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently integrating operation circuits with memory blocks of varying structures, such as 2-dimensional and 3-dimensional configurations, which affects the electrical coupling and operation of memory strings and transistors.
Innovation Solution
The semiconductor device employs alternately stacked insulating and conductive layers in parallel configurations, with specific wiring structures to electrically couple conductive layers within and between different stacked structures, allowing for efficient connection to operation circuits, thereby facilitating program, erase, and read operations in memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory blocks with different structures (2D and 3D) are integrated into a semiconductor memory device, then the device can support diverse memory configurations and improve adaptability, but the complexity of integrating operation circuits with varying memory block structures increases
Solution Approach 1:
The patent implements a universal operation circuit design that can interface with both 2D and 3D memory block structures through standardized wiring structures. The operation circuit is configured to work with multiple memory block types by using common electrical coupling mechanisms, allowing one operation circuit to serve multiple functions across different memory architectures without requiring separate dedicated circuits for each memory type.
Solution Approach 2:
The patent divides the memory device into distinct memory blocks (2D and 3D) that can be independently configured and integrated. Each memory block maintains its own stacked structure characteristics while being connected to the shared operation circuit through standardized interfaces. This segmentation allows flexible integration of different memory types without requiring the entire device to be redesigned for each configuration.
2Reliability
If wiring structures are designed to electrically couple conductive layers in multiple stacked structures, then the electrical coupling efficiency improves, but the wiring structure complexity and area requirements increase
Solution Approach 1:
The patent merges the electrical coupling functions for multiple stacked structures into unified wiring structures. Instead of creating separate wiring paths for each stacked structure, the design combines these functions into shared wiring that can electrically couple conductive layers across different stacked structures simultaneously. This reduces the total number of wiring elements and simplifies the overall wiring architecture while maintaining reliable electrical connections.
Solution Approach 2:
The patent utilizes vertical stacking of conductive layers and wiring structures to achieve three-dimensional electrical coupling. By transitioning from planar two-dimensional wiring to three-dimensional stacked wiring configurations, the design enables efficient electrical coupling between multiple stacked structures without requiring extensive lateral wiring space. The vertical dimension provides additional routing paths that reduce wiring complexity.
3Area of stationary object
If operation circuits are integrated closer to memory blocks to reduce area, then the device footprint decreases, but the difficulty of designing universal interfaces for different memory block structures increases
Solution Approach 1:
The operation circuit is designed with universal interface capabilities that can accommodate both 2D and 3D memory block structures. The same operation circuit implementation can interface with different memory block types through standardized connection protocols and wiring structures, eliminating the need for separate operation circuit designs for each memory type and reducing overall device area.
4Quantity of substance
If stacked structures with alternately stacked insulating and conductive layers are used, then the memory density increases, but the manufacturing precision requirements for layer alignment increase
Solution Approach 1:
The patent segments the memory structure into multiple discrete stacked structures, each consisting of alternately stacked insulating and conductive layers. This segmentation allows for modular manufacturing where each stack can be formed and aligned independently, then combined into the final three-dimensional memory array. The segmented approach reduces the cumulative alignment complexity compared to forming a single large stacked structure.
Data Source
AI summary
A semiconductor device includes a first set of stacked structures including alternately stacked insulating layers and conductive layers disposed on a substrate, and arranged in a generally parallel configuration with respect to each other, a second set of stacked structures including alternately stacked insulating layers and conductive layers disposed on the substrate between the first stacked structures, and arranged in a generally parallel configuration with respect to each other, a first wiring structure configured to electrically couple conductive layers located on the same layer in different stacked structures of the first set of stacked structures, a second wiring structure configured to electrically couple conductive layers located on the same layer in different stacked structures of the second set of stacked structures, and a third wiring structure configured to electrically couple the first wiring structure and the second wiring structure with an operation circuit.