Semiconductor Device with Stacked Memory and Controller
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Solution Overview
Problem
The challenge in semiconductor device design is to minimize size and thickness while increasing storage capacity and speed, as larger chip sizes due to memory chip stacking and tighter design rules make it difficult to accommodate controller chips and memory chips efficiently without increasing the package size, and existing spacer chip techniques increase manufacturing costs and device height.
Innovation Solution
The semiconductor device design incorporates a substrate with multiple semiconductor elements, resin elements, and bonding wires, where memory chips are stacked with a controller chip positioned between them, using adhesive layers and bonding wires to optimize layout and reduce thickness, eliminating the need for spacer chips and allowing for efficient high-density chip arrangement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory chips are stacked in a stair stepped shape to increase storage capacity, then storage capacity is improved, but the planar size of the semiconductor device increases
Solution Approach 1:
The patent implements a nested stacking arrangement where memory chips are vertically stacked one above another in alignment, rather than in a stair-stepped configuration. Multiple memory chips (first, second, third memory chips) are positioned at different heights along the vertical axis while maintaining horizontal alignment, creating a tower-like structure that maximizes vertical space utilization and reduces the planar footprint of the device.
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional vertical stacking configuration. By utilizing the vertical dimension (Z-axis) for chip placement and connecting them through intermediate substrates and wiring layers, the design achieves high storage capacity without expanding the horizontal area (X-Y plane), effectively moving the scaling problem into the third dimension.
2Quantity of substance
If the chip size increases to accommodate more memory chips, then storage capacity is improved, but it becomes difficult to accommodate the controller chip and memory chip adjacent to each other on a substrate
Solution Approach 1:
The patent divides the semiconductor device into multiple independent functional modules: controller chips, memory chips, and intermediate substrate chips. Each chip maintains its own substrate and is positioned at a specific height level. This segmentation allows each component to be optimized independently while simplifying the overall arrangement, as chips connect vertically through standardized interfaces on intermediate substrates rather than requiring complex lateral integration.
Solution Approach 2:
The patent resolves the layout conflict by transitioning from a planar arrangement to a vertical three-dimensional configuration. Controller chips and memory chips are positioned at different vertical levels and connected through intermediate substrates and wiring layers, eliminating the need for them to be adjacent on the same substrate plane. This vertical separation simplifies the horizontal layout requirements while maintaining functional connectivity.
3Reliability
If a spacer chip is used to prevent interference between controller chip and memory chip, then chip interference is prevented, but manufacturing cost increases due to additional processes
Solution Approach 1:
The patent employs intermediate substrate chips that serve multiple functions simultaneously: they provide mechanical support and spacing between chips at different heights, establish electrical connections through wiring layers, and enable vertical stacking integration. These multi-functional intermediate substrates eliminate the need for dedicated spacer chips, reducing the total component count and simplifying the manufacturing process while maintaining proper chip spacing and alignment.
Solution Approach 2:
The patent merges the functions of spacing, support, and electrical connection into integrated intermediate substrate structures. Rather than using separate spacer chips for mechanical separation and additional wiring for electrical connection, the intermediate substrates combine these functions in a single component, reducing the number of discrete parts and assembly steps required, thereby lowering manufacturing complexity and cost.
4Ease of operation
If a spacer chip is used to position memory chip above controller chip, then proper positioning is achieved, but device height increases
Solution Approach 1:
The patent implements adjustable and optimized vertical spacing between chips through the intermediate substrate design. The height and thickness of intermediate substrates can be varied to achieve optimal positioning without requiring excessive vertical space. This dynamic adjustment of spacing allows for compact vertical integration while maintaining proper alignment and connection between controller chips and memory chips at different levels.
Solution Approach 2:
The patent utilizes thin intermediate substrate films and wiring layers to achieve proper chip positioning with minimal vertical thickness. By employing thin-film technologies for the intermediate substrates and connection layers, the design maintains adequate spacing for electrical connections and mechanical support while minimizing the overall device height, avoiding the excessive thickness that would result from traditional thick spacer chips.
Data Source
AI summary
A semiconductor device of an embodiment includes a substrate, first, second, third, and fourth semiconductor elements, a first wiring layer, and first and second bonding wires. The third semiconductor element is on the substrate between the first resin element and the second resin element. The first wiring layer is on the first semiconductor element, is connected to the first semiconductor element, and is connected to the substrate by the first bonding wire. The fourth semiconductor element is on the first wiring layer and is connected to the first wiring layer by a second bonding wire. The first bonding wire is at a side of the first wiring layer other than a side farthest from the second wiring layer.