Semiconductor Device Stacked Memory Wiring Equalization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor modules with multiple memory and data processor chips, existing technologies face challenges in equalizing wiring lengths and reducing noise from crosstalk and capacitive coupling, particularly as operating speeds increase and voltages decrease, affecting data, address, and strobe signal wirings.
Innovation Solution
The solution involves a stacked configuration of memory chips on a module board with address and data system bonding pads arranged in alternating sequences, using common and individual wirings to connect these pads, and employing separate wiring layers and shielding for data and strobe signal paths to minimize noise interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If memory chips and data processor chips are mounted on a module board with conventional wiring layouts, then the device can be assembled, but wiring length equalization between data and address systems becomes difficult, leading to signal timing issues
Solution Approach 1:
The patent transitions from planar wiring layouts to three-dimensional stacked chip architecture. Memory chips are stacked vertically on the module board, allowing wiring to be routed through multiple layers and dimensions. This vertical stacking enables equalization of wiring lengths for both data and address systems by utilizing the Z-dimension, where corresponding bonding pads on stacked chips can be connected through aligned via holes and conductive layers, achieving length equalization without complex planar routing.
Solution Approach 2:
The patent segments the wiring system into separate data system wiring and address system wiring paths. By providing dedicated wiring layers and routing paths for each system, the design allows independent optimization of each wiring type. Data wiring can be routed through specific layers while address wiring uses other layers, enabling precise control over each wiring path's length and characteristics, thus achieving equalization without forcing a single complex routing solution.
2Reliability
If bonding wires are used to connect chips on the module board, then connections can be established, but crosstalk noise and capacitive coupling noise between adjacent wires increases, affecting signal integrity
Solution Approach 1:
The patent moves wiring connections from a two-dimensional planar arrangement to a three-dimensional stacked configuration. Bonding wires connect corresponding bonding pads vertically through stacked chips rather than horizontally across the module board surface. This vertical arrangement in the Z-dimension naturally increases spacing between adjacent signal wires, reducing electromagnetic coupling and crosstalk. The stacked architecture allows signal wires to be positioned at different vertical levels, further isolating them from each other.
Solution Approach 2:
The patent introduces ground wires as intermediary elements positioned between signal wires in the stacked chip configuration. These ground wires act as shielding barriers that electrically isolate adjacent signal lines, reducing capacitive coupling and crosstalk noise. The ground wires are connected to ground potential, creating a reference plane that prevents noise propagation between neighboring data and address signal lines while maintaining signal integrity.
3Speed
If operating speed is accelerated and operating voltage is lowered, then device performance improves, but noise sensitivity increases and wiring length equalization becomes more critical
Solution Approach 1:
The stacked chip architecture utilizes vertical wiring paths through multiple chip layers, enabling precise control over signal path lengths. By designing the stacking sequence and via hole positions, the patent achieves equalization of wiring lengths for high-speed data and address signals, ensuring simultaneous arrival at destination pads. This dimensional approach to wiring design is critical for maintaining signal timing integrity at accelerated operating speeds where nanosecond-level precision is required.
Solution Approach 2:
Ground wires serve as intermediary shielding elements that protect high-speed signal lines from noise interference. Positioned between adjacent signal wires, these ground connections create electromagnetic shielding that reduces crosstalk and capacitive coupling. This shielding mechanism is particularly important for low-voltage, high-speed operations where signal margins are narrow and noise resistance is critical for maintaining reliability.
Data Source
AI summary
There is provided a semiconductor device which makes equalization of wirings between address system chips easy and reduce the influence of crosstalk noise and capacitive coupling noise among data system wirings for connecting the chips. There are mounted, on a module board, a plurality of stacked memory chips which a data processor chip simultaneously accesses. Address system bonding pads to which a plurality of memory chips correspond are commonly coupled by a wire to a bonding lead at one end of the module board wiring whose other end is coupled by a wire to an address system bonding pads of the data processor. Data system bonding pads of the data processor chip are individually coupled to data system bonding pads of the memory chip. With respect to an arrangement of the plurality of data system bonding pads of the data processor chip, an arrangement of the data system bonding pads to which the memory chip, coupled by the data system wiring, corresponds is made such that memory chips are disposed in an alternating sequence.