Semiconductor Device 3D Stacked Metal Wiring
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Solution Overview
Problem
The existing DMOS transistor semiconductor devices face a trade-off between high breakdown voltage and low on-resistance, with wiring resistance being a significant challenge due to limitations in wiring width and burial capability, making it difficult to reduce on-resistance without compromising breakdown voltage.
Innovation Solution
The semiconductor device employs a configuration with thicker metal wiring layers and wider wiring widths in specific areas, eliminating interlayer insulation films to increase the sectional area of the wiring, thereby reducing wiring resistance while maintaining high breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the wiring width is increased to reduce wiring resistance, then the on-resistance is reduced, but the breakdown voltage cannot be maintained
Solution Approach 1:
The patent transitions from planar wiring (2D) to three-dimensional stacked wiring structure (3D) by forming upper and lower wirings in different layers connected through via holes. This dimensional change increases the effective cross-sectional area for current flow without increasing the planar footprint, thereby reducing wiring resistance while preserving the breakdown voltage characteristics of the underlying semiconductor structure.
Solution Approach 2:
The patent implements nested wiring structures where upper wirings are positioned above and connected to lower wirings through via holes, creating a hierarchical three-dimensional wiring architecture. This nesting approach allows multiple wiring paths to occupy overlapping vertical spaces, effectively increasing the total conductive cross-section without expanding the lateral device dimensions.
2Reliability
If the wiring width is increased to reduce wiring resistance, then the on-resistance is reduced, but the device area increases
Solution Approach 1:
The patent utilizes the vertical dimension by stacking wirings in multiple layers (upper wiring layer and lower wiring layer) connected via via holes. This three-dimensional wiring architecture increases the effective wiring cross-sectional area for current conduction without proportionally increasing the lateral device footprint, thus reducing on-resistance while maintaining compact device area.
3Loss of energy
If thicker metal wiring layers are used to reduce wiring resistance, then the wiring resistance is reduced, but the manufacturing complexity increases
Solution Approach 1:
The patent divides the wiring structure into segmented components: lower wirings in a first wiring layer, via holes connecting to upper wirings in a second wiring layer, and intermediate insulation layers. This segmentation allows each component to be manufactured using standard semiconductor fabrication processes, making the overall thicker wiring structure achievable without requiring complex single-step manufacturing techniques.
Solution Approach 2:
The patent employs nested wiring structures where upper wirings are positioned above and connected to lower wirings through via holes, creating a hierarchical three-dimensional wiring architecture. This nesting approach allows multiple wiring paths to occupy overlapping vertical spaces, effectively increasing the total conductive cross-section without expanding the lateral device dimensions.
Data Source
AI summary
The semiconductor device according to one embodiment of the present invention includes: a semiconductor substrate; and a first area and a second area which are respectively provided on the semiconductor substrate. The first area includes: a first metal wiring formed in a first wiring layer above the semiconductor substrate and having a certain first width; a second metal wiring formed in a second wiring layer located in an upper layer of the first wiring layer and having the first width; and a first contact connecting the first metal wiring and the second metal wiring and having a second width equal to or less than the first width. The second area includes a third metal wiring having a film thickness from the first wiring layer to the second wiring layer and having a certain third width.