Semiconductor Stacked Module via Wire Bond Chip Selection
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Solution Overview
Problem
High-density semiconductor devices face challenges in forming multiple vias or spreading conductive pastes evenly without contacting other circuits, and achieving reliable insulation between chip selection signal lines and other circuits, which negatively impacts integration density and reliability.
Innovation Solution
A semiconductor device design featuring a substrate with a circuit, pads, and terminals, where switching elements control electrical signals between pads and the circuit, and through electrodes pass through the substrate to isolate pads, allowing for reliable chip selection and I/O signal transmission without reducing integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple vias or conductive pastes are formed on high-density semiconductor devices, then electrical connections between stacked chips can be established, but it becomes difficult to form them evenly without contacting other circuits and achieving reliable insulation
Solution Approach 1:
The patent transitions from planar via formation to three-dimensional wire bonding. By routing connections through the air space above the device rather than through the substrate, it avoids the manufacturing difficulties of forming multiple vias in high-density configurations while maintaining reliable electrical connections and insulation between stacked chips.
Solution Approach 2:
The patent introduces wire bonds as intermediary elements that connect pads between stacked chips. These wire bonds serve as mediators that establish electrical connections without requiring direct via formation through the substrate, thereby avoiding contact with other circuits and achieving reliable insulation in high-density configurations.
2Adaptability or versatility
If chip selection signal lines are allotted additional area within semiconductor devices, then chip selection functionality can be implemented, but integration density is negatively impacted
Solution Approach 1:
The patent moves chip selection signal transmission from the planar substrate level to the vertical dimension using wire bonds. This allows chip selection functionality to be implemented without consuming additional substrate area, as the signal lines are routed through the three-dimensional space above the device rather than occupying precious substrate real estate.
Solution Approach 2:
The patent uses flexible wire bonds to transmit chip selection signals between stacked chips. These thin, flexible conductors can be routed through limited spaces without requiring additional substrate area, enabling chip selection capability while maintaining high integration density on the substrate.
3Reliability
If switching elements are installed between pads and circuits, then reliable insulation and noise reduction can be achieved, but device complexity increases
Solution Approach 1:
The patent extracts the switching function from integrated circuit elements and implements it using discrete wire bonds that can be selectively connected or disconnected. This externalization of the switching function provides reliable signal isolation and noise reduction while avoiding the complexity of integrating switching elements within the circuit substrate.
Solution Approach 2:
The patent uses wire bonds as intermediary elements that can act as physical switches between pads and circuits. By controlling the presence or connection state of these wire bond intermediaries, reliable signal isolation and noise reduction are achieved without requiring complex integrated switching circuitry, thereby managing device complexity.
Data Source
AI summary
A semiconductor device in which a plurality of chips can be reliably stacked without reducing integration thereof. The semiconductor device includes a substrate on which a circuit is provided. Pads are disposed on the substrate for testing the circuit. At least one terminal is provided on the substrate. First conductors are used to electrically couple the pads and the circuit. Second conductors are used to electrically couple the at least one terminal and the circuit. A switching element is disposed in the middle of the first conductors to control the electrical connection between the pads and the circuit. A plurality of semiconductor devices may be stacked on top of one another to form a stacked module, wherein chip selection lines are formed, which extend to the bottom of each of the semiconductor devices to electrically couple chip selection terminals from among the at least one terminal of the semiconductor devices.