Semiconductor Stacked Components Embedded Support Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor device stacks face limitations in accommodating components of varying dimensions and establishing flexible electrical connections, particularly when the second chip is larger than the first chip or vice versa, due to restrictive packaging arrangements.
Innovation Solution
A semiconductor device design featuring a support layer with embedded first components, an intermediate electrical connection network, and vias connecting to external means, allowing for flexible placement and connection of second components, with optional additional connection networks and zones on the support layer for enhanced connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the first chip is mounted on an electrical connection plate with the second chip bonded directly to it, then electrical connections can be established, but the arrangement is not suitable when the second chip is larger than the first chip
Solution Approach 1:
The patent transitions from a planar mounting arrangement to a three-dimensional stacked configuration with the first chip embedded in the support layer and the second chip mounted above it. This vertical dimensionality change allows the second chip to be larger than the first chip while maintaining compact packaging and establishing electrical connections through vias and interconnection layers.
2Length of moving object
If electrical connection pads are placed on the periphery of the second chip and connected via electrical connection wires, then connections can be made, but the second chip is necessarily smaller than the first chip
Solution Approach 1:
The patent introduces an intermediate layer with an electrical connection network as a mediator between the first chip and the second chip. This intermediate network, formed through vias passing through the support layer, provides flexible routing options that allow the second chip to be larger than the first chip while maintaining manageable connection complexity.
3Adaptability or versatility
If chips are encapsulated in a package mounted on the plate, then protection and connection are provided, but freedom in component dimensions is restricted
Solution Approach 1:
The patent segments the device into distinct functional layers: a support layer containing the embedded first chip, an intermediate layer with electrical connection networks and vias, and a top layer with the second chip. This segmentation allows each layer to be optimized independently for its specific function, providing freedom in component dimensions while maintaining manufacturing feasibility through standardized layering processes.
Data Source
AI summary
A semiconductor device includes at least one first component (5) (for example, a first integrated circuit), having a front face provided with electrical connection pads. The first component is embedded in a support layer (2) is a position such that the front face of the first component is not covered and lies parallel to a first face of the support layer. An intermediate layer (8) is formed on the front face of the first component and on the first face of the support layer. An electrical connection network (9) within the intermediate layer selectively connects to the electrical connection pads of the first component. The device further includes at least one second component (11) (for example, a second integrate circuit, having one face placed above the intermediate layer and provided with electrical connection pads selectively connected to the electrical connection network. Electrical connection vias (17) pass through the support layer and selectively connect the electrical connection network to an external electrical connection formed on a second face of the support layer.