Semiconductor Package With Stacked Through-Vias for Reduced Voltage Drop
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Solution Overview
Problem
Semiconductor packages face challenges in minimizing voltage drop, switching time, and occupied area due to congestion in integrated circuits, particularly in ultra-fine pitch designs where input/output and power circuits increase congestion.
Innovation Solution
The solution involves a semiconductor package configuration where a second semiconductor chip handles input/output signals and a third semiconductor chip supplies power directly to a first semiconductor chip, reducing congestion by positioning these chips on the rear surface of the first chip, thereby decreasing voltage drop and switching time while minimizing occupied area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If input/output circuits and power circuits are integrated on the same semiconductor chip, then circuit functionality is complete, but voltage drop increases and switching time increases due to congestion
Solution Approach 1:
The patent divides the semiconductor package into multiple separate chips: a first chip containing the first integrated circuit, a second chip containing input/output circuits, and a third chip containing power circuits. This segmentation separates previously congested circuits into distinct physical locations, reducing interference and improving electrical performance.
Solution Approach 2:
The patent transitions from a two-dimensional planar integration approach to a three-dimensional stacked architecture. Multiple chips are arranged vertically and connected through through-vias, utilizing the vertical dimension to reduce congestion while maintaining compact footprint.
2Adaptability or versatility
If more circuits are integrated on the same chip, then functionality increases, but occupied area increases
Solution Approach 1:
The patent employs a three-dimensional stacked chip architecture where multiple functional chips are arranged vertically and connected through through-vias. This approach maintains high circuit functionality while minimizing the horizontal occupied area by utilizing the vertical dimension for integration.
Solution Approach 2:
The patent implements a nested structure where the second chip and third chip are positioned on opposite sides of the first chip, with all chips interconnected through through-vias. This nested arrangement maximizes space utilization and reduces the overall package footprint.
3Reliability
If input/output circuits and power circuits are separated into different chips, then voltage drop decreases, but device complexity increases
Solution Approach 1:
The patent segments the package into specialized chips: the first chip with the integrated circuit, the second chip with input/output circuits, and the third chip with power circuits. This segmentation reduces voltage drop by eliminating congested current paths while the modular structure manages complexity through functional separation.
Solution Approach 2:
The through-vias serve multiple functions: they provide electrical connection between chips, enable signal transmission, and support the stacked architecture. This multi-functionality reduces the need for additional specialized components, managing overall device complexity.
Data Source
AI summary
A semiconductor package including a first semiconductor chip including a first semiconductor layer having a first forward surface having a first integrated circuit thereon and a first rear surface and a plurality of first through vias electrically connected to the first integrated circuit and including at least first and second groups of first through vias, a second semiconductor chip including a second integrated circuit electrically connected to the first group of first through vias, and a third semiconductor chip including third through vias electrically connected to the second group of first through vias, wherein the first group of first through vias transfer input/output signals of the first integrated circuit, and the second group of first through vias transfer power to the first integrated circuit, may be provided.