Semiconductor Package Stacked-Via Polymer Residue Removal
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Solution Overview
Problem
Conventional stacked-via structures in semiconductor packages face issues with polymer residue, leading to open circuits or high resistance, which increases manufacturing costs due to the need for additional processes to remove the residue.
Innovation Solution
A semiconductor package design that includes a passivation layer with a through hole defined by sidewalls, where a seed layer is disposed between conductive layers, and a second passivation layer is bonded to the first, allowing for the exposure and deposition of conductive layers to avoid polymer residue issues, enhancing electrical conductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional stacked-via structures are fabricated, then integration density is improved, but polymer residue causes open circuits or high resistance
Solution Approach 1:
The patent extracts and removes the problematic polymer residue through additional etching processes. The method involves performing a first etching process to form vias, then conducting a second etching process specifically targeted at removing polymer residue from the via walls, thereby eliminating the harmful substance that causes open circuits and high resistance while preserving the beneficial stacked-via structure for high integration density.
2Reliability
If extra processes are used to remove polymer residue, then electrical conductance is improved, but manufacturing cost increases
Solution Approach 1:
The patent changes the parameters of the etching process by introducing a second etching step with different conditions (such as different chemistry, time, or power settings) optimized specifically for removing polymer residue. This parameter change enables selective removal of the harmful polymer material while minimizing damage to the conductive layers, thereby improving electrical conductance without requiring completely additional process modules that would significantly increase manufacturing cost.
3Productivity
If stacked-via structures are used, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the via formation process with the polymer residue removal process by integrating a second etching step into the existing stacked-via fabrication sequence. Rather than treating these as separate, independent processes, the method combines them into a unified manufacturing flow where the second etching is performed immediately after via formation, thereby reducing the total number of discrete process modules and simplifying the overall manufacturing complexity while maintaining high integration density benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design reduces manufacturing costs and improves electrical conductance by minimizing polymer residue and shortening the conductive path within the semiconductor package, thereby enhancing the integration density and performance of semiconductor structures.
Implementation Method 1
patterning the first passivation layer to define a first hole
Implementation Method 2
patterning the first passivation layer to define a first hole
Implementation Method 3
disposing a first conductive layer on the first seed layer
Implementation Method 4
disposing a second conductive layer on the exposed first seed layer through the second hole
Implementation Method 5
providing a second passivation layer that is bonded to the first passivation layer
Data Source
AI summary
A method of manufacturing a semiconductor package includes: (1) providing a first passivation layer on a carrier; (2) patterning the first passivation layer to define a first hole; (3) disposing a first seed layer on the first hole; (4) disposing a first conductive layer on the first seed layer; (5) replacing the carrier with a second passivation layer; (6) patterning the second passivation layer to define a second hole exposing the first seed layer; and (7) disposing a second conductive layer on the exposed first seed layer through the second hole.