3D Semiconductor Package Stacking with Conformal Dielectric Coating
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating small form factor, high-density packages with stacked semiconductor dice at a reasonable cost and acceptable yield for applications like smartphones, laptops, and IoT devices, particularly for packages combining memory, logic, and RF dice.
Innovation Solution
The method involves thinning a silicon wafer, forming dielectric bond lines, and stacking singulated semiconductor dice with conductive pillars, using dielectric materials to connect and secure the dice, and applying a conformal coating to reduce package height and eliminate the need for encapsulation, enabling efficient and precise assembly of multiple dice in a compact form factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional packaging methods are used, then manufacturing process is simple, but package footprint and height are large
Solution Approach 1:
The patent transitions from conventional 2D planar packaging to 3D vertical stacking architecture. Multiple semiconductor dice are stacked vertically with through-silicon vias (TSVs) enabling inter-layer electrical connections, thereby reducing package footprint by utilizing the vertical dimension for integration.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor dice are stacked within a single package footprint. Each die is positioned vertically above another, with TSVs providing electrical pathways through the stacked structure, effectively nesting multiple functional layers within a compact volume.
2Adaptability or versatility
If more semiconductor dice are stacked to increase density, then package functionality increases, but manufacturing yield decreases
Solution Approach 1:
The patent performs preliminary testing and characterization of semiconductor dice before stacking. Known good dice are selected and prepared in advance, with TSVs pre-formed and electrical connections pre-established, thereby ensuring high reliability and yield in the final stacked package.
Solution Approach 2:
The patent introduces an intermediary carrier substrate or reflow carrier that facilitates the stacking process. This intermediary structure enables precise alignment and temporary support during assembly, allowing multiple dice to be stacked with high precision while maintaining manufacturing yield.
3Length of stationary object
If package height is reduced for compact form factor, then integration density increases, but conventional encapsulation becomes problematic
Solution Approach 1:
The patent extracts or eliminates the conventional encapsulation mold compound from the packaging process. Instead of using traditional molding encapsulation, the patent employs alternative protection methods such as thin conformal dielectric coatings applied directly to the stacked dice, thereby achieving compact height while maintaining device protection.
Solution Approach 2:
The patent replaces bulky encapsulation with thin conformal dielectric film coatings that provide protection while minimizing height increase. These thin films conformally coat the stacked dice structure, providing environmental protection and mechanical support without the height penalty of conventional molding.
Data Source
AI summary
Methods of forming semiconductor device packages comprising stacking multiple dice, the die stack exhibiting thin bond lines and having an outer environmental coating, the bond lines and environmental coating comprising an in situ formed compound. Semiconductor device packages so formed and electronic systems incorporating such packages are also disclosed.